Forum Discussion
Occasional ContributorTriple-Speed Ethernet IP for Agilex 5 fails during Quartus Synthesis
Hi,
I am using the IP core version 12.0.0. of the Triple-Speed Ethernet IP in the configuration PCS only with LVDS "transceivers" & HPS adapter. The target FPGA is an Agilex 5 namely the A5ED043AB32AE3V. The IP core issues an error during Analysis & Synthesis in Quartus Pro 2026.1.
Error(18842): The ENABLE port on clock gate i_altera_pcs_pma_1g_hps|eth_tse_0|hps_gmii_adapter_instance|u_pcs_rx_clk_gated|altclkctrl_comp|altclkctrl_inst|clkena_inst is connected to a constant. It must be driven by a real signal.
I checked the generated netlists. The error occurs in an encrypted section; thus I can not change anything. The usage of the IP core is straight forward. Connect to the Platform Designer project of the HPS, where I fed out EMAC0.
There is nothing I can change during generation of the IP core nor its instantiation. For me this looks like (another) Agilex 5 bug.
Regards
Gerhard
4 Replies
GerhardCadekHi,
I recently learned this forum is now the Altera "support". Now, I reported an issue with an Altera IP core generated by Quartus that fails Synthesis. And there is no answer nor suggestion on that? Really? If you provide me/us the unecnrypted net list we will help ourself and correct the error.
Regards
Gerhard
paveetirrasrie_AlteraFrequent Contributor
Hello Gerhard,
Apologies for the delayed response.
Your configuration (PCS only, LVDS I/O, HPS adapter, EMAC0 exported as GMII) sounds consistent with the supported use case, so the error is almost certainly inside the encrypted IP logic itself.
Quick check, are you referring to this reference design?: https://altera-fpga.github.io/rel-26.1/embedded-designs/agilex-5/common/tsn/sgmii_lvds/sgmii_lvds/?h=
- GerhardCadek
Hi,
thank you for your response. Yes that reference design is exactly what I am doing in my design here. I generated the TSE PCS/PMA IP core for the target device with the HPS bridge and connected it to the exported EMAC0 signals. I traced the IP core source down to the file where the error is reported. Unfortunately this file is encrypted so I cannot read it nor apply a patch there. I can try to reduce my design to just HPS with EMAC export and the PCS/PMA IP core and provide you a quartus archive if this helps you to trace the issue.
Best regards
Gerhard
- GerhardCadek
Hi,
due to unknown reasons I cannot pürovide you any attachments via the forum. That's somewhat strange. I uploaded the Quartus Archive onto our web server in a hidden directory. You can download it here:
https://www.oreganosystems.at/application/files/1217/8565/2140/pcspma1g_bug20260802.qar.zip
Simply remove he ".zip" appendix from the file name.
Regards
Gerhard
