Triple-Speed Ethernet IP for Agilex 5 fails during Quartus Synthesis

Hi,

I am using the IP core version 12.0.0. of the Triple-Speed Ethernet IP in the configuration PCS only with LVDS "transceivers" & HPS adapter. The target FPGA is an Agilex 5 namely the  A5ED043AB32AE3V. The IP core issues an error during Analysis & Synthesis in Quartus Pro 2026.1. 

Error(18842): The ENABLE port on clock gate i_altera_pcs_pma_1g_hps|eth_tse_0|hps_gmii_adapter_instance|u_pcs_rx_clk_gated|altclkctrl_comp|altclkctrl_inst|clkena_inst is connected to a constant. It must be driven by a real signal.

I checked the generated netlists. The error occurs in an encrypted section; thus I can not change anything. The usage of the IP core is straight forward. Connect to the Platform Designer project of the HPS, where I fed out EMAC0.

There is nothing I can change during generation of the IP core nor its instantiation. For me this looks like (another) Agilex 5 bug.

Regards

Gerhard