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GerhardCadek
Occasional Contributor
Occasional ContributorTriple-Speed Ethernet IP for Agilex 5 fails during Quartus Synthesis
Hi, I am using the IP core version 12.0.0. of the Triple-Speed Ethernet IP in the configuration PCS only with LVDS "transceivers" & HPS adapter. The target FPGA is an Agilex 5 namely the A5ED043AB3...
paveetirrasrie_Altera
Frequent Contributor
Frequent ContributorHello Gerhard,
Apologies for the delayed response.
Your configuration (PCS only, LVDS I/O, HPS adapter, EMAC0 exported as GMII) sounds consistent with the supported use case, so the error is almost certainly inside the encrypted IP logic itself.
Quick check, are you referring to this reference design?: https://altera-fpga.github.io/rel-26.1/embedded-designs/agilex-5/common/tsn/sgmii_lvds/sgmii_lvds/?h=
