Stratix 10 fPLL is cascade source mode doesn't lock

Hello everyone.

I use fPLL cascading with Stratix 10 FPGA: fPLL in cascade source mode is connected to fPLL in transceiver mode.

In my design reference clock for fPLL in cascade source mode is not stable after power-up and I apply user recalibration to it. But after user recalibration when reference clock is stable, fPLL doesn't set lock signal.

After some investigation of the issue, I found that my design works fine with Quartus Pro 21.2 but doesn't work with newer versions like Quartus Pro 23.4/25.1/26.1.

Is there any known issue about fPLL is cascade source mode?

Any suggestions about how to overcome this issue are welcomed.