Forum Discussion
New ContributorStratix 10 fPLL is cascade source mode doesn't lock
Regular ContributorHi,
Thanks for sharing the design. I have made some observations and have few questions regarding your design.
1) Why do you need a cascade clock to drive the transceivers? Though supported, cascading the PLL insert jitter. Why not use direct clock input pin for the reference clock?
2) The downstream xcvr_tr_fpll, is configured for Transceiver mode and has 2 refclk sources. One 100MHz from clock pin and other from the upstream fPLL which provides 156.25MHz. As the frequencies vary you have to reconfigure the fPLL to adapt to the frequency settings. In the design the IP is set to 100MHz only. Are you doing this?
Regards,
Altera Support
New ContributorHello.
- Why do you need a cascade clock to drive the transceivers? Though supported, cascading the PLL insert jitter. Why not use direct clock input pin for the reference clock?
This is needed because of the requirements for my actual project. I can't share the details of why I really need it. Let's just accept it.
2) The downstream xcvr_tr_fpll, is configured for Transceiver mode and has 2 refclk sources. One 100MHz from clock pin and other from the upstream fPLL which provides 156.25MHz. As the frequencies vary you have to reconfigure the fPLL to adapt to the frequency settings. In the design the IP is set to 100MHz only. Are you doing this?
The shared design is simplified version of my real design that I cannot share. In real design transceiver fPLL is reconfigured and recalibrated after rate changing and clock switchover.
- Ash_R_Altera
Hi,
Ok, let's accept the requirement in point #1.
Point #2, can you at least provide the steps that you follow in detail from power-up -> reconfiguration -> recalibration -> user ready. Which registers are you using etc. details will be helpful.
Regards
- rtldeseng
Hello.
Let's concentrate on test project that I can share. It can reproduce the issue that I am talking about.
I changed the project (see the one attached to the message). Now it can reconfigure transceiver fPLL (xcvr_tr_fpll) and it use either reference fixed clock or clock from cascade source fPLL (xcvr_cs_fpll).
After power-up, XCVRs and xcvr_tr_fpll are calibrated using fixed reference clock (100MHz). xcvr_cs_fpll is calibrated using clock from RX XCVR but it is not stable, so lock signal is not stable too.
The steps to reconfigure using clock from xcvr_cs_fpll:
- Set lock to ref. for RX XCVR.
- Assertiong of reset to TX XCVR.
- Recalibration of xcvr_cs_fpll
- Reconfiguration of xcvr_tr_fpll (setting pre-reconfig bit, changing reference clock muxer, changing dividers, etc.)
- Recalibration of xcvr_tr_fpll.
- Deassertiong of reset to TX XCVR
If project was compiled with Quartus Pro 21.2, after step 6, lock signals of fPLLs are stable, clock that comes from TX XCVR is equal to expected value (156.25MHz)
If project was compiled with Quartus Pro 23.4 or 25.3 there are no lock on fPLLs outputs and as a consequence no stable clock from TX XCVR.
So, the result depends on Quartus version.
cs_fpll_controller.sv recalibrates xcvr_cs_fpll.
tr_fpll_controller.sv reconfigures and recalibrates xcvr_tr_fpll (the registers used for reconfiguration can be found as localparams).
- Ash_R_Altera
Hi,
Did you get a chance to go through my earlier comment?
Regards,
Altera Tech Support
- Ash_R_Altera
Hi,
Sorry for the late response. After doing analysis on the code, I found one critical issue.File: tr_fpll_controller.sv
Following line of code:
// We set only bit[1] (mask 0x2)
o_avmm_m_writedata <= {read_data_buf[7:1], 1'b1};In the FSM_PRECAL_WR_PRE_RECONFIG state, the code writes to register 0x100 to set bit[1] (the calibration request bit), but the expression is wrong:
The concatenation {read_data_buf[7:1], 1'b1} places the literal 1 at bit position 0 (the LSB), not bit 1. Contrast this with the correct version in FSM_CONF_WR_CAL_BIT further down in the same FSM:
State Expression Bit actually set
FSM_PRECAL_WR_PRE_RECONFIG {read_data_buf[7:1], 1'b1} bit[0] ← wrong
FSM_CONF_WR_CAL_BIT {read_data_buf[7:2], 1'b1, read_data_buf[0]} bit[1] ← correct
Per the Stratix 10 Transceiver PHY UG, bit[1] of register 0x100 is the calibration trigger for an fPLL. The pre-calibration phase fails to arm this bit, so the downstream recalibration sequence is broken — the PreSICE never sees a valid calibration request, and the FPLL will not re-lock after the reference clock switch.Please correct it to the following:
o_avmm_m_writedata <= {read_data_buf[7:2], 1'b1, read_data_buf[0]}; // correctly sets bit[1]
Can you please check this part?
Regards,
Altera Tech Support
dncmrc1Occasional Contributor
Hi,
rtldeseng is not working for us anymore.
Thanks for your finding.
We tested your modifications but it didn't change the outcome: the shared project works only if compiled with Quartus 21.1.
Any hints?
Regards,
Marco
