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rtldeseng's avatar
rtldeseng
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1 month ago

Stratix 10 fPLL is cascade source mode doesn't lock

Hello everyone. I use fPLL cascading with Stratix 10 FPGA: fPLL in cascade source mode is connected to fPLL in transceiver mode. In my design reference clock for fPLL in cascade source mode is not ...
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Transceiver
Ash_R_Altera's avatar
Ash_R_Altera
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21 days ago

Hi,

Thanks for sharing the design. I have made some observations and have few questions regarding your design.

1) Why do you need a cascade clock to drive the transceivers? Though supported, cascading the PLL insert jitter. Why not use direct clock input pin for the reference clock?

2) The downstream xcvr_tr_fpll, is configured for Transceiver mode and has 2 refclk sources. One 100MHz from clock pin and other from the upstream fPLL which provides 156.25MHz. As the frequencies vary you have to reconfigure the fPLL to adapt to the frequency settings. In the design the IP is set to 100MHz only. Are you doing this?

Regards,

Altera Support

rtldeseng's avatar
rtldeseng
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21 days ago

Hello.

  1. Why do you need a cascade clock to drive the transceivers? Though supported, cascading the PLL insert jitter. Why not use direct clock input pin for the reference clock?

This is needed because of the requirements for my actual project. I can't share the details of why I really need it. Let's just accept it.

2) The downstream xcvr_tr_fpll, is configured for Transceiver mode and has 2 refclk sources. One 100MHz from clock pin and other from the upstream fPLL which provides 156.25MHz. As the frequencies vary you have to reconfigure the fPLL to adapt to the frequency settings. In the design the IP is set to 100MHz only. Are you doing this?

The shared design is simplified version of my real design that I cannot share. In real design transceiver fPLL is reconfigured and recalibrated after rate changing and clock switchover.

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    20 days ago

    Hi,

    Ok, let's accept the requirement in point #1. 

    Point #2, can you at least provide the steps that you follow in detail from power-up -> reconfiguration -> recalibration -> user ready. Which registers are you using etc. details will be helpful.

     

    Regards

    • rtldeseng's avatar
      rtldeseng
      Icon for New Contributor rankNew Contributor
      18 days ago

      Hello.

      Let's concentrate on test project that I can share. It can reproduce the issue that I am talking about.

      I changed the project (see the one attached to the message). Now it can reconfigure transceiver fPLL (xcvr_tr_fpll) and it use either reference fixed clock or clock from cascade source fPLL (xcvr_cs_fpll).

      After power-up, XCVRs and xcvr_tr_fpll are calibrated using fixed reference clock (100MHz). xcvr_cs_fpll is calibrated using clock from RX XCVR but it is not stable, so lock signal is not stable too.

      The steps to reconfigure using clock from xcvr_cs_fpll:

      1. Set lock to ref. for RX XCVR.
      2. Assertiong of reset to TX XCVR.
      3. Recalibration of xcvr_cs_fpll
      4. Reconfiguration of xcvr_tr_fpll (setting pre-reconfig bit, changing reference clock muxer, changing dividers, etc.)
      5. Recalibration of xcvr_tr_fpll.
      6. Deassertiong of reset to TX XCVR

      If project was compiled with Quartus Pro 21.2, after step 6, lock signals of fPLLs are stable, clock that comes from TX XCVR is equal to expected value (156.25MHz)

      If project was compiled with Quartus Pro 23.4 or 25.3 there are no lock on fPLLs outputs and as a consequence no stable clock from TX XCVR.

      So, the result depends on Quartus version.

      cs_fpll_controller.sv recalibrates xcvr_cs_fpll.

      tr_fpll_controller.sv reconfigures and recalibrates xcvr_tr_fpll (the registers used for reconfiguration can be found as localparams).