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rtldeseng's avatar
rtldeseng
Icon for New Contributor rankNew Contributor
2 months ago

Stratix 10 fPLL is cascade source mode doesn't lock

Hello everyone. I use fPLL cascading with Stratix 10 FPGA: fPLL in cascade source mode is connected to fPLL in transceiver mode. In my design reference clock for fPLL in cascade source mode is not ...
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Transceiver
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
2 months ago

Hi,

Just checking if you can provide some more inputs as asked in my previous comment?

 

Regards