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rtldeseng's avatar
rtldeseng
Icon for New Contributor rankNew Contributor
2 months ago

Stratix 10 fPLL is cascade source mode doesn't lock

Hello everyone. I use fPLL cascading with Stratix 10 FPGA: fPLL in cascade source mode is connected to fPLL in transceiver mode. In my design reference clock for fPLL in cascade source mode is not ...
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Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
2 months ago

Hi,

Can you please provide few details about your design?

1) What is the input clock frequency and source of it?

2) What is the output frequency that you are trying to achieve?

3) Is the create_clock constraint applied for the input clock at the top level?

 

Few design implementation checks would be:

1) You must recalibrate the PLL when the reference clock is available.

2) Clock on OSC_CLK_1 signal is used for calibration of the fPLL and it must be stable. Is it true for your case?

 

It would be easier to debug if you can provide a reference design to reproduce the issue.

 

Regards