Can an Application Ignore PCIe flow Control Credits?

I'm using a Cyclone V GT with PCIe core using Gen 1 Avalon-ST 64-bit endpoint interface. Occasionally packet sending would stall and I had thought it was because I was ignoring the flow control credits. But after properly handling tx_st_ready going low, the problem seems to have gone away. 

So the question is can I ignore the flow control signals as long as I throttle the sending when tx_st_ready goes low?

In the flow control section of the UG-011110 dated 2020.06.02, it says

That is not important for our application. But then after spending several paragraphs explaining how the PCIe Hard IP tracks and checks credits, it make says:

Can I assume that is only in the case described in the yellow highlight?

Also, in the flow control update loop description, is says:

Is that where the Hard IP is lowering tx_st_ready so the App is indirectly handling credits? 

If so, one odd thing is that sometimes tx_st_ready does not go low until toward the end of a packet write (ie closer to the EOP and the SOP). I would think it would do the credit check as soon as it had the TLP headers which contain the type, number of dwords etc. 

Just a suggestion, but for Apps that did want to optimize throughput, it would have been helpful to just expose the credit limits to the App instead of making it independently keep track of them. The credit system is a bit confusing.