F-tile 10GE Ethernet Reference Design ISSP Error

Hello,

I am currently a master's student and apart of the research I am working on at my lab involves implementing a subsection of the O-RAN 5G fronthaul interface on an Agilex 7 FPGA, which will depends on the F-Tile Ethernet Hard IP.

I have been working with the 10GE F-Tile Ethernet Hard IP reference design and have successfully compiled the design, programmed the generated image onto the FPGA, and accessed the provided test utilities through Quartus System Console.

However, I am encountering issues when running the serial loopback test. On the initial attempts, the test runs but reports packet mismatches and ultimately fails. On subsequent attempts, I receive errors indicating a value mismatch involving an ISSP probe. I would appreciate additional guidance on troubleshooting the ISSP probe mismatch.

I have also observed that rx_pcs_ready does not assert during testing, which appears to indicate an issue with the RX path. I am unsure whether this is directly related to the ISSP probe issue or represents an additional problem with the RX configuration or link initialization.

Could you provide guidance on how to diagnose and resolve the ISSP probe value mismatch, as well as what conditions are required for rx_pcs_ready to assert in the 10GE F-Tile reference design?

Specifications:
- Quartus Prime Pro 24.1
- jtagd 24.1 executable was replaced with jtagd 25.1 version to allow USB Blaster III support (The specific board I am using mentions to do this in their BSP) 

-  Device model: AGFB027R24C2E2V

% run_test
--- Turning off packet generation ---- -------- Printing PHY status ---------
------------------------------------ --------------------------------------

-------- Enabling loopback ----------
--------------------------------------

Applying Rx Reset

Reading Loop Back Register Status

reg1_xcvr0 0x00062340

reg2_xcvr0 0x00062340

Loop Back for Lane 3 ..

Writing 1st loopback data for Lane 3

Reading Loop Back Registers

reg1_xcvr0 lane 3 0x0006a340

reg2_xcvr0 lane 3 0x0006a340

Writing 2nd loopback data for Lane 3

Reading Loop Back Registers

reg1_xcvr0 lane 3 0x00062340

reg2_xcvr0 lane 3 0x00062340

Releasing Rx Reset

Checking Status of the Flux Register

lane 0 0x00000000

lane 1 0x00000000

lane 2 0x00000000

lane 3 0x00000000

--- Wait for RX clock to settle... ---
--------------------------------------

RX PHY Register Access: Checking Clock Frequencies (KHz)

TXCLK :402840 (KHZ)
RXCLK :161130 (KHZ)

TX PLL Lock Status 0x00000001

Rx Frequency Lock Status 0x00000000

RX PCS Ready 0x0

TX Lanes Stable 0x1

Deskewed Status 0x0

Link Fault Status 0x00000001

Rx Frame Error 0xdeadc0de

Rx AM LOCK Condition 0xdeadc0de

Value from issp reset probe is 0xed/0b11101101
ERROR:rx_pcs_ready is not asserted or link fault is detected. Expected value from issp reset probe is : 0xff

---------------- Done ----------------

Thank you for any guidance you can provide