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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

Agilex-7 AXI MCDMA for PCIe hang

Hi! 

I'm working with AGIB023R18A1E1VC device and having issues with AXI Multichanned DMA IP for PCIe.

Since I require a PCIe bridge, I configured the IP in MCDMA+BAS+BAM mode (PCIe Gen 4, 512-bit), generated an example design, and integrated the subsystem into my project. Although I do not use MCDMA, I rely heavily on the BAS and BAM functionality.

The issue I’m seeing is that writing more than 448 bytes to the BAS causes the host to hang and subsequently reset. Notably, between the write transaction and the host reset, the FPGA internal logic is still able to write to the BAS, indicating no hang on the AXI bus. There are no issues with read transactions.

 

 

 

 

 

 

 

 

 

We observe this issue not with only one card. At first we run into it in Q25.1 but still have it in Q25.3.1

If you need some captures from the signal tap or any additional details I may provide them.

Thank you in advance! Mikhail.

Pcie

11 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 month ago

    Hi Mikhail_a 

    Thanks for reaching out.
    May I ask the following to help us understand the issue:

    1. Could you attach the AXI MCDMA .ip file so we can review the parameter settings?
    2. Which design example variant and which driver did you use?
    3. Is the issue first observed in Q25.1, then in Q25.3.1? Did it work correctly prior to Q25.1?
    4. Are you using an Altera Dev Kit or a custom board?
    5. Could you share the STP when the issue occurs?
    6. Could you provide the exact steps to reproduce the issue?

     

    Thanks.
    Best Regards,
    Ven 

  • Mikhail_a's avatar
    Mikhail_a
    Icon for Occasional Contributor rankOccasional Contributor
    1 month ago

    Hi VenT_Altera​ 

    1. Could you attach the AXI MCDMA .ip file so we can review the parameter settings?

    I will attach an archive with the whole subsystem we use

    1. Which design example variant and which driver did you use?

    Unfortunately I don't remember what particular example design we used. We use our own driver for our device, but it does nothing with PCIe itself.

    1. Is the issue first observed in Q25.1, then in Q25.3.1? Did it work correctly prior to Q25.1?

    There was no AXI MCDMA for PCIe before 25.1 version. At least it was the first version where we started to use this IP core.

    1. Are you using an Altera Dev Kit or a custom board?

    We use Bittware IA-440i board

    1. Could you share the STP when the issue occurs?

    Not at the moment, but we see no protocol errors there.

    1. Could you provide the exact steps to reproduce the issue?

    One may just create an example design for BAS+BAM mode and then try to write 449 bytes to BAS. With the subsustem in attachments it should not take much time.

    • VenT_Altera's avatar
      VenT_Altera
      Icon for Frequent Contributor rankFrequent Contributor
      1 month ago

      Hi Mikhail_a 

      Thank you for your reply.


      Since you are using your own driver and application, to isolate whether the issue is software or hardware, please run our Example Design on your board. Port the Example Design to your platform and run the accompanying application. Follow the steps in the user guide to generate Example Design and run the application. https://docs.altera.com/r/docs/817911/25.3.1/axi-multichannel-dma-ip-for-pci-express-user-guide/functional-description?tocId=ak5zOaugZ0426etSxKRO0Q
      You may generate the AXI-MM DMA Example Design and use the Custom or DPDK driver to perform the perfq_app or mcdma_test: AXI-MM DMA test. Please share your test results.

      Also, could you share the design goal for your implementation? If MCDMA is not required, you might consider using BAM + BAS (user mode) to simplify the design.

      Thanks.
      Best Regards,
      Ven 

      • VenT_Altera's avatar
        VenT_Altera
        Icon for Frequent Contributor rankFrequent Contributor
        1 month ago

        Hi Mikhail_a 

        I understand that you observed the failure in Example Design as well. Let's focus on the Example Design. Please provide the log from the prerequisites setup to running the application and hit the errors. I'd like to see the exact commands and their output. Which driver (Custom or DPDK) and which AXI-MM DMA test did you perform (perfq_app or mcdma_test)? Please share the detailed steps in the log.  

        Thanks.
        Best Regards,
        Ven 

  • Mikhail_a's avatar
    Mikhail_a
    Icon for Occasional Contributor rankOccasional Contributor
    1 month ago

    Hi VenT_Altera​ 

    We have already done running the example design and the result was positive. But we also found out that example design writes or reads number of bythes that is multiple of data bus width, and we run into the same issue when modified it and made it send 449, 450 and so on number of bytes.

    We had the same issue in both MCDMA+BAS+BAM and BAS+BAM modes. But we need the first option as only in that configuration having user MSI-X and user FLR is possible.

    Best,
    Mikhail