Agilex-7 AXI MCDMA for PCIe hang

Hi Mikhail_a 

Thank you for your reply.

Since you are using your own driver and application, to isolate whether the issue is software or hardware, please run our Example Design on your board. Port the Example Design to your platform and run the accompanying application. Follow the steps in the user guide to generate Example Design and run the application. https://docs.altera.com/r/docs/817911/25.3.1/axi-multichannel-dma-ip-for-pci-express-user-guide/functional-description?tocId=ak5zOaugZ0426etSxKRO0Q
You may generate the AXI-MM DMA Example Design and use the Custom or DPDK driver to perform the perfq_app or mcdma_test: AXI-MM DMA test. Please share your test results.

Also, could you share the design goal for your implementation? If MCDMA is not required, you might consider using BAM + BAS (user mode) to simplify the design.

Thanks.
Best Regards,
Ven 

Hi Mikhail_a,

Could you please confirm the Design Example variant, user mode, application test, and the exact steps/commands you used to reproduce the error? This will help me to set up the same environment and replicate the error. It would also be helpful if you could provide the log that captures all the commands and their outputs.

Thanks.
Best Regards,
Ven

Hi Mikhail_a,

Thanks for the detailed description. Based on what you've shared, the following points are very likely contributing to the hang you're observing with 449-byte payloads in your BAS-based custom TG.

1. BAS Address/Payload Alignment Requirement

With your Gen4 x16 configuration, the AXI-MM data width is 512 bits (64 bytes). The Bursting Slave's addresses must be aligned to the width of the data bus — for example, if the data width is 64B, the addresses must align to 64B.

449 bytes is not a multiple of 64 bytes, which immediately violates this constraint. Your custom TG needs to ensure that both the start address and the transfer length are 64-byte aligned for the BAS interface at Gen4 x16 (512-bit data width).

Note that, in the design example, the burst size is set to 256 bytes. Therefore the BAS transfer size must be a multiple of 256 bytes.

2. "Enable Address Byte Aligned Transfer" Is Not Supported

The "Enable address byte aligned transfer" option has a value of Off and default of Off — this option is not supported in the current release. AXI Multichannel DMA IP for PCI Express* User Guide There is a documented known issue associated with this: when address byte aligned transfers are enabled, a DMA failure may be observed for lower payload sizes on the AXI interface. Byte aligned access is not supported — address should be aligned to the data width.

So even if you were to attempt byte-aligned operation, the IP doesn't support it, and using non-aligned transfers risks exactly the DMA failure / hang you're seeing.

You may round your custom TG's transfer sizes up to the nearest 64-byte boundary (e.g., 449 → 512 bytes), and ensure the start address is also 64-byte aligned.

If you can set up SignalTap on the BAS write address channel (bas_axi_mm_awaddr, bas_axi_mm_awvalid, bas_axi_mm_awready, bas_axi_mm_awlen) and the write response channel (bas_axi_mm_bvalid, bas_axi_mm_bresp), that would confirm whether the hang occurs at address acceptance or at the write response phase. But fixing the alignment to 64B first is the most direct next step.

Thanks.

Best Regards,

Ven