R_Tile PCIE

I am using Quartus 26.1 and Questa 2024.1 to simulate the PCIe IP example. The selected IP is R-Tile Avalon Streaming IP for PCI Express. The example design is generated in PIPE mode. I slightly modified the example driver to make the EP transmit 100 MWr TLPs with 128-byte payload each and 100 MRd TLPs with 128-byte payload each.

Currently issues occur with the CplD responses from the RP. In the 100-packet test, 96 out of 100 CplD packets have correct payload data, while 4 packets show data mismatch. The faulty packets are not fully corrupted. Their first three payload beats are valid, yet the final 256-bit beat turns into all zeros.

There is another issue. When modifying the EP to send MWr TLPs longer than 128 bytes to the RP in the example design, no CplD frames will be responded by the RP after transmitting subsequent MRd TLPs.