Forum Discussion
GerhardCadek
Occasional Contributor
Occasional ContributorTriple-Speed Ethernet IP for Agilex 5 fails during Quartus Synthesis
Hi, I am using the IP core version 12.0.0. of the Triple-Speed Ethernet IP in the configuration PCS only with LVDS "transceivers" & HPS adapter. The target FPGA is an Agilex 5 namely the A5ED043AB3...
GerhardCadekOccasional Contributor
Occasional ContributorHi,
due to unknown reasons I cannot pürovide you any attachments via the forum. That's somewhat strange. I uploaded the Quartus Archive onto our web server in a hidden directory. You can download it here:
https://www.oreganosystems.at/application/files/1217/8565/2140/pcspma1g_bug20260802.qar.zip
Simply remove he ".zip" appendix from the file name.
Regards
Gerhard
