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GerhardCadek
Occasional Contributor
Occasional ContributorTriple-Speed Ethernet IP for Agilex 5 fails during Quartus Synthesis
Hi, I am using the IP core version 12.0.0. of the Triple-Speed Ethernet IP in the configuration PCS only with LVDS "transceivers" & HPS adapter. The target FPGA is an Agilex 5 namely the A5ED043AB3...
GerhardCadekOccasional Contributor
Occasional ContributorHi,
thank you for your response. Yes that reference design is exactly what I am doing in my design here. I generated the TSE PCS/PMA IP core for the target device with the HPS bridge and connected it to the exported EMAC0 signals. I traced the IP core source down to the file where the error is reported. Unfortunately this file is encrypted so I cannot read it nor apply a patch there. I can try to reduce my design to just HPS with EMAC export and the PCS/PMA IP core and provide you a quartus archive if this helps you to trace the issue.
Best regards
Gerhard
