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GerhardCadek's avatar
GerhardCadek
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6 days ago

Triple-Speed Ethernet IP for Agilex 5 fails during Quartus Synthesis

Hi, I am using the IP core version 12.0.0. of the Triple-Speed Ethernet IP in the configuration PCS only with LVDS "transceivers" & HPS adapter. The target FPGA is an Agilex 5 namely the  A5ED043AB3...
Ethernet
GerhardCadek's avatar
GerhardCadek
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2 hours ago

Hi,

I recently learned this forum is now the Altera "support". Now, I reported an issue with an Altera IP core generated by Quartus that fails Synthesis. And there is no answer nor suggestion on that? Really? If you provide me/us the unecnrypted net list we will help ourself and correct the error. 

Regards

Gerhard