Forum Discussion

GerhardCadek's avatar
GerhardCadek
Icon for Occasional Contributor rankOccasional Contributor
1 month ago
Solved

Agilex 5 Reset Sequencer - Design Assitant reports IPC-40038 violation

Hi, I am using 2x25Gbit PCS/PMA function only (with FEC) and 2x10Gbit PCS/PMA function only (without FEC) in my Agilex 5 design (device A5ED043AB32AE3V, Quartus Pro 26.1). 25Gbit transceiver are usi...
Ethernet
Transceiver
  • Ash_R_Altera's avatar
    Ash_R_Altera
    25 days ago

    Hi,

    I have checked with the internal team. The warning against the rule IPC-40038 can be ignored safely.

     

    Regards

GerhardCadek's avatar
GerhardCadek
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

Hi,

yes, I am using the IP core exactly this way as shown in the figure. As both PCS/PMA functions reside within the same bank, there is one pma_cu_clk output signal from the Reset Sequencer IP driving both PCS/PMA units.

Regards

Gerhard

  • Ash_R_Altera's avatar
    Ash_R_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi,

    I am confused here a bit. Yes, PCS and PMA can reside in the same bank. But, as you have different banks 4C and 1C on right and left side respectively, there should be two reset sequencer IPs in your design. Each IPs pma_cu_clk port should connect to the PHY IP as shown in the diagram. Is that so in your design?

     

    Regards