How to Prevent Agilex 7 F-tile PMA Direct PHY TX Lane Skew
Hi, We are implementing a 16-lane custom 1.0125 Gbps TX with F-tile PMA Direct PHY IP. The 16 lanes should be bonded together and they need to have a skew of less than 0.05 UI. However, we simulated the TX and found the serial output of each lane had skew of up to 11 ns, despite the fact that they had sychronized parallel input data. We have followed the suggested settings in user guide to enable system bonding, such as Number of Lanes=16, PMA Width=16, and Selected tx_clkout clock source=Bond Clock. For IP port connection, we use tx_clkout[0] as the source of all 16 tx_coreclkin. We also use it to clock all 16 parallel input data of TX in FPGA core fabric to make sure they are synchronized. Our IP Parameter and waveform is as attched. In testbench we feed parallel input data to all 16 lanes at the same time. We also assert TX PMA Interface Data Valid bit [38]. However, the serial output of each lane seems to start at different point of time, creating skew. Is this model behavior or actual hardware behavior? We tested on development board and our target sink is unable to lock to TX serial output as expected. Is there any way to eliminate the skew? Below is quartus version and our target board. Quartus Version : 25.3 Target Board : AGIC040R39A2E2VR0 Thanks wentsung8Views0likes0CommentsRegarding the TX settings of MIPI CSI2 IP
In my Qsys project, I want to implement a function where the Test Pattern Generator IP sends the pattern to the MIPI CSI2 TX via an AXI stream. The MIPI CSI2 TX then sends the pixel data to link1 of the MIPI DPHE. After looping back, link0 of the MIPI DPHE sends the data to the MIPI CSI2 RX via the MIPI interface. However, strangely, the MIPI CSI2 TX axi stream ready signal remains low, and it doesn't process axi stream data from the TPG. The MIPI CSI2 TX settings are shown in the figure. What could be causing this phenomenon? Any help is appreciated.130Views0likes10CommentsAbout Dual Simplex for Agilex 3
In the" GTS Transceiver Dual Simplex Interfaces User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs", Note 3 in Table 2, Section 2. Overview, states the following: "DS mode is not currently supported for Agilex™ 3 FPGAs for this protocol." Which future version of Quartus Prime will support Agilex 3 ? https://www.intel.com/content/www/us/en/docs/programmable/825853/25-1/overview.html45Views0likes2CommentsFitter cannot ...
I am trying to set up a basic SDI transmitter on an Agilex 5. Currently, my setup is a 148.5 MHz refclk, a GTS PMA Direct PHY IP configured for 12G SDI, a GTS Reset Sequencer, and a GTS System PLL configured to take in the refclk and output 742.5 MHz (this is based on the minimum system PLL frequency recommendation in the SDI II IP documentation). I have my serial output differential pair on pins BE129 and BE126 which are the GTS Left 1B TX 0 channels, and my refclk coming in as a differential pair on pins AY120 and AY115 which are the refclk pins for GTS Left 1B. According to the documentation for the SoM, these refclk pins should be configured to 148.5 MHz. For some reason, when I try to compile, the fitter fails in the plan stage with error 14566 "The Fitter cannot place 1 periphery component due to conflicts with existing constraints (1 I/O pad). Fix the errors described in the submessages, and then rerun the Fitter." The submessages read, "Illegal constraint of I/O pad to the location PIN_AY115" (175019), "No legal location could be found out of 1 considered location. Reasons why each location could not be used are summarized below:" (16234), "There is no routing connectivity between the I/O pad and the destination I/O input buffer" (175006), "The I/O pad could not be placed in any location to satisfy its connectivity requirements" (175022), and "The destination I/O input buffer could not be placed in any location to satisfy its connectivity requirements" (175022). There isn't very much logic surrounding the system (basically just a counter to create some dummy input data), so I'm not sure why it wouldn't be able to connect specifically the n side of the refclk. Has anyone encountered similar issues/errors and could maybe point me in the right direction? Any help would be appreciated.41Views0likes4CommentsAbout Design Limitations and Known Issues
In the "GTS SDI II IP User Guide", section 8. Design Limitations and Known Issues states a known issue: "High bit error rates are observed in recovered data." It also states that there is no workaround in the current version of Quartus, but are there any plans to address this issue? https://www.intel.com/content/www/us/en/docs/programmable/823539/25-3/design-limitations-and-known-issues.html45Views0likes3CommentsPlease let me know how to get a GTS license for Agilex 5.
I have already some licenses, for example, IP-SDI-II, IP-DP, IP-HDMI and so on. I want to use these IP on Agilex 5. However, Ordering Code is not match the IPs I have when I searched the IP User Guide. SDI => IP-GTS-SDI-II Display Port => IP-GTS-DP Is it possible to get a License of IP-GTS-xxx, if I regenerate in my SSLC ? Or, Need I buy the new licenses for GTS Transceiver? Thanks.Solved32Views0likes2CommentsDelay in SPI-to-Avalon-MM IP Response After MAX10 Reset
Hello everyone, I’m using the SPI-to-Avalon-MM IP to enable communication between an external microcontroller (MSP430) and a MAX10 FPGA (MAX10M50DAF256CG). In my setup, the microcontroller acts as the SPI master, and the FPGA is the slave. The microcontroller also controls a GPIO line connected to a load switch, allowing it to power the MAX10 on or off. The FPGA receives a 26 MHz external oscillator input, which feeds into a PLL. The PLL’s lock signal is used to generate a system reset. Here’s the behavior I’m observing: even after the PLL lock signal asserts and the system leaves reset (measured by routing the lock signal to an external FPGA pin and timing from the moment CONF_DONE goes high), it still takes around 9 ms before the FPGA and the SPI-to-Avalon-MM IP start responding to SPI messages from the microcontroller. My questions are: What could be causing this post-reset delay? Is there a defined startup time for the FPGA and IP to begin responding? I haven’t found documentation on this—are there any relevant resources? Thanks in advance for your help.Solved1.2KViews0likes6CommentsHDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi support, When creating a design with "HDMI Intel FPGA IP" having significant values as: - Direction: Receiver - Enable Active Video Protocol: AXIS-VVP Full - Support FRL: Untick (disabled) Then Quartus 24.3 Pro Build 212 (newest) fails in Analysis & Synthesis with the errors: Error(13224): Verilog HDL or VHDL error at hdmi_rx_core_altera_hdmi_1975_ozylggi.v(771): index 2 is out of range [1:0] for 'cv_vid_de' Error: Failed to elaborate design: Error: Flow failed: Errors generated during elaboration Error: Quartus Prime Synthesis was unsuccessful. 3 errors, 0 warnings Archived project is attached. Question: Is there any known fix or workaround for this problem? Regards M_DK_FPGA PS. It appears that an internal non-designer assigned value PIXELS_PER_CLOCK is assigned to 8, as for FRL enabled, thus causing an internal loop to go out of range.Solved6.4KViews0likes38Comments