GTS SDI II IP Core...what is the tx_vid_clkout frequency
I'm using an Agelix 5 (the Altera development board) with Quartus Pro 25.3.1 w/patch 1.02. i'm trying to set-up the GTS SDI II IP Core (version 2.3.0) on the Main screen, the only configurable values are: Video Standard = HD-SDI Direction = Transmitter Insert payload ID = off SDI_II wrapper = Both BASE and PHY everything else is grayed out. I have connected the tx_pll_refclk to the 148.5MHz input. I do see the tx_pll_locked signal behave as expected and it does lock. the problem is when I look at the tx_vid_clkout signal its 58.3MHz. I expected it to be 74.25MHz. I'm somewhat confused as to whether tx_pll_refclk should be 148.5MHz or 74.25MHz, but if the 148.5 is wrong then I would have expected tx_vid_clkout to be twice, not a somewhat random value of 58.3MHz. when I reconfigured the IP core for 3G-SDI, the tx_vid_clkout frequency doubled to 116MHz. The doubling would be what I expected, but still a wrong frequency. i'm not sure what i'm setting wrong and why i'm getting a clkout of 58.3MHz
Regarding the TX settings of MIPI CSI2 IP
In my Qsys project, I want to implement a function where the Test Pattern Generator IP sends the pattern to the MIPI CSI2 TX via an AXI stream. The MIPI CSI2 TX then sends the pixel data to link1 of the MIPI DPHE. After looping back, link0 of the MIPI DPHE sends the data to the MIPI CSI2 RX via the MIPI interface. However, strangely, the MIPI CSI2 TX axi stream ready signal remains low, and it doesn't process axi stream data from the TPG. The MIPI CSI2 TX settings are shown in the figure. What could be causing this phenomenon? Any help is appreciated.
How to Prevent Agilex 7 F-tile PMA Direct PHY TX Lane Skew
Hi, We are implementing a 16-lane custom 1.0125 Gbps TX with F-tile PMA Direct PHY IP. The 16 lanes should be bonded together and they need to have a skew of less than 0.05 UI. However, we simulated the TX and found the serial output of each lane had skew of up to 11 ns, despite the fact that they had sychronized parallel input data. We have followed the suggested settings in user guide to enable system bonding, such as Number of Lanes=16, PMA Width=16, and Selected tx_clkout clock source=Bond Clock. For IP port connection, we use tx_clkout[0] as the source of all 16 tx_coreclkin. We also use it to clock all 16 parallel input data of TX in FPGA core fabric to make sure they are synchronized. Our IP Parameter and waveform is as attched. In testbench we feed parallel input data to all 16 lanes at the same time. We also assert TX PMA Interface Data Valid bit [38]. However, the serial output of each lane seems to start at different point of time, creating skew. Is this model behavior or actual hardware behavior? We tested on development board and our target sink is unable to lock to TX serial output as expected. Is there any way to eliminate the skew? Below is quartus version and our target board. Quartus Version : 25.3 Target Board : AGIC040R39A2E2VR0 Thanks wentsungAbout Dual Simplex for Agilex 3
In the" GTS Transceiver Dual Simplex Interfaces User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs", Note 3 in Table 2, Section 2. Overview, states the following: "DS mode is not currently supported for Agilex™ 3 FPGAs for this protocol." Which future version of Quartus Prime will support Agilex 3 ？ https://www.intel.com/content/www/us/en/docs/programmable/825853/25-1/overview.htmlFitter cannot ...
I am trying to set up a basic SDI transmitter on an Agilex 5. Currently, my setup is a 148.5 MHz refclk, a GTS PMA Direct PHY IP configured for 12G SDI, a GTS Reset Sequencer, and a GTS System PLL configured to take in the refclk and output 742.5 MHz (this is based on the minimum system PLL frequency recommendation in the SDI II IP documentation). I have my serial output differential pair on pins BE129 and BE126 which are the GTS Left 1B TX 0 channels, and my refclk coming in as a differential pair on pins AY120 and AY115 which are the refclk pins for GTS Left 1B. According to the documentation for the SoM, these refclk pins should be configured to 148.5 MHz. For some reason, when I try to compile, the fitter fails in the plan stage with error 14566 "The Fitter cannot place 1 periphery component due to conflicts with existing constraints (1 I/O pad). Fix the errors described in the submessages, and then rerun the Fitter." The submessages read, "Illegal constraint of I/O pad to the location PIN_AY115" (175019), "No legal location could be found out of 1 considered location. Reasons why each location could not be used are summarized below:" (16234), "There is no routing connectivity between the I/O pad and the destination I/O input buffer" (175006), "The I/O pad could not be placed in any location to satisfy its connectivity requirements" (175022), and "The destination I/O input buffer could not be placed in any location to satisfy its connectivity requirements" (175022). There isn't very much logic surrounding the system (basically just a counter to create some dummy input data), so I'm not sure why it wouldn't be able to connect specifically the n side of the refclk. Has anyone encountered similar issues/errors and could maybe point me in the right direction? Any help would be appreciated.About Design Limitations and Known Issues
In the "GTS SDI II IP User Guide", section 8. Design Limitations and Known Issues states a known issue: "High bit error rates are observed in recovered data." It also states that there is no workaround in the current version of Quartus, but are there any plans to address this issue? https://www.intel.com/content/www/us/en/docs/programmable/823539/25-3/design-limitations-and-known-issues.html
