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wentsung's avatar
wentsung
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1 month ago

How to Prevent Agilex 7 F-tile PMA Direct PHY TX Lane Skew

Hi, We are implementing a 16-lane custom 1.0125 Gbps TX with F-tile PMA Direct PHY IP. The 16 lanes should be bonded together and they need to have a skew of less than 0.05 UI. However, we simulated...
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CheepinC_altera's avatar
CheepinC_altera
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1 month ago

Hi,

 

As I understand it, you observe skew issue at the TX serial data output in your 16 lane F-Tile DPHY. Thanks for sharing the IP parameter screenshots. By the way, seems like I could not locate the waveform file attachment. Can you try zipping it and share again? If you could share simple simulation folder with steps to run the simulation, that would be very helpful.

 

Thank you.   

wentsung's avatar
wentsung
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1 month ago

Hi,

Thanks for your reply. Seems like I could not attach zip files in the post, so I send you message instead. To simplify the setup, we reduce TX lane count to two, yet the TX output remains skewed. The Simulator we use is Cadence Xcelium (xrun), so you might run into some problem. Nonetheless, it would be nice if you could review pin connection for us. 

 

Best regards,

Wentsung