How to Prevent Agilex 7 F-tile PMA Direct PHY TX Lane Skew
Hi, We are implementing a 16-lane custom 1.0125 Gbps TX with F-tile PMA Direct PHY IP. The 16 lanes should be bonded together and they need to have a skew of less than 0.05 UI. However, we simulated the TX and found the serial output of each lane had skew of up to 11 ns, despite the fact that they had sychronized parallel input data. We have followed the suggested settings in user guide to enable system bonding, such as Number of Lanes=16, PMA Width=16, and Selected tx_clkout clock source=Bond Clock. For IP port connection, we use tx_clkout[0] as the source of all 16 tx_coreclkin. We also use it to clock all 16 parallel input data of TX in FPGA core fabric to make sure they are synchronized. Our IP Parameter and waveform is as attched. In testbench we feed parallel input data to all 16 lanes at the same time. We also assert TX PMA Interface Data Valid bit [38]. However, the serial output of each lane seems to start at different point of time, creating skew. Is this model behavior or actual hardware behavior? We tested on development board and our target sink is unable to lock to TX serial output as expected. Is there any way to eliminate the skew? Below is quartus version and our target board. Quartus Version : 25.3 Target Board : AGIC040R39A2E2VR0 Thanks wentsung
Stratix-10G FPGA Transceiver Configuration for Ethernet MAC 100G Controller
Hi, We need to validate our custom built Ethernet MAC 100G controller core on Stratix-10G FPGA. We are planning to use the in-built FPGA transceiver for the PHY functionality. From the IP catalog, we selected "L-Tile/H-Tile Transceiver Native PHY Stratix 10 IP" and tried to configure for Ethernet MAC 100G. But we couldn't find any preset configuration which supports either 100G or 25G line rate. Could you pl. suggest what preset configuration to be used? Pl. note that our Ethernet MAC 100G controller core supports 256-bit data path. Thanks, Sunil
Agilex 5 GTS Supported Protocols
Hi Altera/Community, I’m trying to better understand the protocols supported by the Agilex 5 GTS transceivers. In the user guide, it mentions that the supported protocol is 10GBase-LR. I wanted to confirm: is 10GBase-R the underlying protocol used before the optical module? Also, does this mean that other optical modules, such as 10GBase-SR, are supported as well? Any clarification on how the transceivers interact with different optical modules would be greatly appreciated. Thanks in advance!
MSGDMA: Is Linux Driver Mandatory? Using devmem2 & F2SDRAM Bridge
Hello everyone, I am currently working on an MSGDMA implementation. I have verified that I can read the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode. I have two specific questions regarding this setup: 1、Is configuring the MSGDMA Linux kernel driver a mandatory condition for the hardware to function correctly? Is it possible to bypass the driver and configure the MSGDMA to start data transfer directly using devmem2 (user-space access)? 2、I noticed that some implementations write to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM link, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?
Dynamic Reconfiguration Support For Our USB3 IP Core In Agilex-5
Hi Altera Team, We are using Agilex 5, and in one of our projects we are implementing the Dynamic Reconfiguration IP. However, we are facing some issues. We are using the GTS transceiver for our USB 3 Soft IP. In a standalone Gen1 design, we received a custom quartus.ini file from your team that enables the i_tx_pma_elecidle_sync and i_txclkdivrate_sync ports only when the clocking mode is configured to PMA clocking mode.It's working fine.However, with this configuration, we are unable to use the System PLL clocking mode. In our project, we are implementing the Dynamic Reconfiguration IP to switch between Gen1 (SuperSpeed) and Gen2 (SuperSpeed Plus). As mentioned above, the Dynamic Reconfiguration IP only supports System PLL clocking mode and does not allow PMA clocking mode. When we set the PMA configuration rule to Basic (or any other option), we are able to configure the transceiver in System PLL clocking mode. However, in this case, the two ports mentioned above are not generated, and these ports are required for USB 3 functionality. We would like to have such quartus.ini file that supports System PLL clocking mode with i_tx_pma_elecidle_sync and i_txclkdivrate_sync ports. Our Resources: Quartus Prime Pro 25.3 and Agilex-5 Premium development kit. Could you please help us resolve this issue or suggest a supported configuration that meets these requirements? Thank you for your support.
Ticket Update
Hi - I have posted a follow up question on an old thread an would appreciate any help! I am making this post, as it is not clear where I can submit an official ticket otherwise. Can be seen here: Transceiver data corruption | Altera Community Please do feel free to delete this post when somone is assigned to the issue. Thanks.Transceiver data corruption
I am trying to externally loopback a simple data-stream using the GTS on the Agilex 5, over an external QSFP loopback module. The GTS is configured as followed: External clock chip: Outputs 156.25 MHz clock verified using an oscilloscope. System PLL: Outputs 125 MHz to the GTS. GTS: Basic PMA Direct System PLL freq: 125 MHz PMA speed: 1250 Mbps PMA width: 10 TX/RX PLL/CDR: 156.25 MHz TX/RX core interface FIFO: single width TX/RX clock: System PLL clock /1 The RTL used to transfer data over TX: module top( input CPU_RESET_n, input REFCLK, output gts_o_tx_serial_data, output gts_o_tx_serial_data_n, input gts_i_rx_serial_data, input gts_i_rx_serial_data_n ); // gts logic gts_pma_cu_clk_i; logic gts_tx_reset, gts_rx_reset; logic gts_tx_reset_ack, gts_rx_reset_ack; logic gts_tx_ready, gts_rx_ready; logic tx_coreclkin, rx_coreclkin; (* noprune *) logic gts_tx_clkout, gts_rx_clkout; logic gts_rs_grant_i; logic gts_rc_rs_req_o; (* noprune *) logic gts_tx_pll_locked /* synthesis keep */; (* noprune *) logic gts_rx_is_lockedtodata /* synthesis keep */; (* noprune *) logic gts_rx_is_lockedtoref /* synthesis keep */; logic o_refclk2core; (* noprune *) logic [79:0] gts_i_tx_parallel_data /* synthesis keep */; (* noprune *) logic [79:0] gts_o_rx_parallel_data /* synthesis keep */; assign gts_pma_cu_clk_i = srcss_bank1_pma_cu_clk_o; assign tx_coreclkin = gts_tx_clkout; assign rx_coreclkin = gts_rx_clkout; assign gts_rs_grant_i = srcss_bank1_rs_grant_o; // reset sequencer signals logic srcss_bank1_rs_grant_o; logic srcss_bank1_rs_priority; logic srcss_bank1_rc_rs_req; logic srcss_bank1_pma_cu_clk_o; assign srcss_bank1_rs_priority = '0; assign srcss_bank1_rc_rs_req = gts_rc_rs_req_o; // system pll signals logic gts_systempll_refclk_rdy; assign gts_systempll_refclk_rdy = 1'b1; gts_top u0 ( // gts .gts_top_clock_bridge_rx_in_clk_clk (QSFP_REFCLK_p), .gts_top_clock_bridge_tx_in_clk_clk (QSFP_REFCLK_p), .intel_directphy_gts_0_i_pma_cu_clk_clk (gts_pma_cu_clk_i), .intel_directphy_gts_0_i_tx_reset_tx_reset (gts_tx_reset), .intel_directphy_gts_0_i_rx_reset_rx_reset (gts_rx_reset), .intel_directphy_gts_0_o_tx_reset_ack_tx_reset_ack (gts_tx_reset_ack), .intel_directphy_gts_0_o_rx_reset_ack_rx_reset_ack (gts_rx_reset_ack), .intel_directphy_gts_0_o_tx_ready_tx_ready (gts_tx_ready), .intel_directphy_gts_0_o_rx_ready_rx_ready (gts_rx_ready), .intel_directphy_gts_0_i_tx_coreclkin_clk (tx_coreclkin), .intel_directphy_gts_0_i_rx_coreclkin_clk (rx_coreclkin), .intel_directphy_gts_0_o_tx_clkout_clk (gts_tx_clkout), .intel_directphy_gts_0_o_rx_clkout_clk (gts_rx_clkout), .intel_directphy_gts_0_i_src_rs_grant_src_rs_grant (gts_rs_grant_i), .intel_directphy_gts_0_o_src_rs_req_src_rs_req (gts_rc_rs_req_o), .intel_directphy_gts_0_o_tx_serial_data_o_tx_serial_data (gts_o_tx_serial_data), .intel_directphy_gts_0_o_tx_serial_data_n_o_tx_serial_data_n (gts_o_tx_serial_data_n), .intel_directphy_gts_0_i_rx_serial_data_i_rx_serial_data (gts_i_rx_serial_data), .intel_directphy_gts_0_i_rx_serial_data_n_i_rx_serial_data_n (gts_i_rx_serial_data_n), .intel_directphy_gts_0_o_tx_pll_locked_o_tx_pll_locked (gts_tx_pll_locked), .intel_directphy_gts_0_o_rx_is_lockedtodata_o_rx_is_lockedtodata (gts_rx_is_lockedtodata), .intel_directphy_gts_0_o_rx_is_lockedtoref_o_rx_is_lockedtoref (gts_rx_is_lockedtoref), .intel_directphy_gts_0_o_refclk2core_o_refclk2core (o_refclk2core), .intel_directphy_gts_0_i_tx_parallel_data_i_tx_parallel_data (gts_i_tx_parallel_data), .intel_directphy_gts_0_o_rx_parallel_data_o_rx_parallel_data (gts_o_rx_parallel_data), // reset sequencer signals .intel_srcss_gts_0_o_src_rs_grant_src_rs_grant (srcss_bank1_rs_grant_o), .intel_srcss_gts_0_i_src_rs_priority_src_rs_priority (srcss_bank1_rs_priority), .intel_srcss_gts_0_i_src_rs_req_src_rs_req (srcss_bank1_rc_rs_req), .intel_srcss_gts_0_o_pma_cu_clk_clk (srcss_bank1_pma_cu_clk_o), // system pll signals .intel_systemclk_gts_0_i_refclk_rdy_data (gts_systempll_refclk_rdy) ); // syncronise reset logic gts_tx_system_reset; altera_reset_synchronizer #( .ASYNC_RESET (1), .DEPTH (2) ) gts_tx_rst_sync ( .reset_in (~CPU_RESET_n), .clk (gts_tx_clkout), .reset_out (gts_tx_system_reset) ); // generate test data stream logic [7:0] counter; logic [7:0] test_stream; always_ff @(posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if (gts_tx_system_reset) begin counter <= 8'b0; test_stream <= 8'b0; end else begin counter <= counter + 1; case (counter) 8'd0: test_stream <= 8'h3C; 8'd1: test_stream <= 8'h7F; 8'd2: test_stream <= 8'h11; 8'd3: test_stream <= 8'h07; default: test_stream <= 8'h00; endcase end end // detect and transform idle data, and mark control symbols logic [7:0] idle_data_transform; logic control_symbol_detect; always_comb begin idle_data_transform = (test_stream == 8'h00) ? 8'hBC : test_stream; control_symbol_detect = (idle_data_transform == 8'h1C) || (idle_data_transform == 8'h3C) || (idle_data_transform == 8'h5C) || (idle_data_transform == 8'h7C) || (idle_data_transform == 8'h9C) || (idle_data_transform == 8'hBC) || (idle_data_transform == 8'hDC) || (idle_data_transform == 8'hFC) || (idle_data_transform == 8'hF7) || (idle_data_transform == 8'hFB) || (idle_data_transform == 8'hFD) || (idle_data_transform == 8'hFE); end // pipline combinational logic to ensure timings are met logic [7:0] idle_data_transform_r; logic control_symbol_detect_r; always_ff @ (posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if(gts_tx_system_reset) begin idle_data_transform_r <= 8'b0; control_symbol_detect_r <= 1'b0; end else begin idle_data_transform_r <= idle_data_transform; control_symbol_detect_r <= control_symbol_detect; end end // --- 8b/10b Encoding --- // https://libsv.readthedocs.io/en/latest/encoder_8b10b.html logic [9:0] encoded_out; logic code_error; encoder_tx encoder_inst ( .i_clk (gts_tx_clkout), .i_reset_n (~gts_tx_system_reset), .i_en (1'b1), .i_8b (idle_data_transform_r), .i_ctrl (control_symbol_detect_r), .o_10b (encoded_out), .o_code_err (code_error) ); // pipeline encoded outputs to ensure timing is met logic [9:0] encoded_out_r; always_ff @(posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if (gts_tx_system_reset) encoded_out_r <= 10'b0; else encoded_out_r <= encoded_out; end // send data over TX logic data_path_rdy_tx; always_ff @(posedge gts_tx_clkout or posedge gts_tx_system_reset) begin if (gts_tx_system_reset) begin gts_i_tx_parallel_data <= 80'b0; data_path_rdy_tx <= 0; end else begin data_path_rdy_tx <= gts_tx_ready && gts_tx_pll_locked; case (data_path_rdy_tx) 1: gts_i_tx_parallel_data <= {1'b1, 39'b0, 1'b0, 1'b1, 28'b0, encoded_out_r}; 0: gts_i_tx_parallel_data <= 80'b0; endcase end end endmodule This RTL passes timing standalone, but when signal tap is used, it does produce warnings. In SignalTap I take the following measurments: Instance TX: data: gts_i_tx_parallel_data[79:0] clock domain: gts_tx_clkout Instance RX: data: gts_i_rx_parallel_data[79:0] clock domain: gts_rx_clkout The issue I am seeing is intermitted failures upon bitstream-re-configure: On the TX side, after the encoder has encoded, the TX data reads as folowed: (EXPECTED): ... 283, 17C, 283, 17C, 183, 335, 0B1, 347, 283, 17C, 283, 17C, ... This is the expected pattern on the RX side (post-framing) However, in my experiments so far, I have found that it only sometimes works: Here are the framing results after 5 different re-flashes: (FAILURE): ... 283, 17C, 283, 17C, 383, 135, 0B1, 347, 083, 37C, 283, 17C, ... (FAILURE): ... 283, 17C, 283, 17C, 383, 135, 0B1, 347, 083, 37C, 283, 17C, ... (FAILURE): ... 283, 17C, 283, 17D, 183, 335, 0B1, 346, 283, 17C, 283, 17C, ... (SUCCESS): ... 283, 17C, 283, 17C, 183, 335, 0B1, 347, 283, 17C, 283, 17C, ... (FAILURE): ... 283, 17C, 283, 175, 1B1, 307, 083, 37C, 283, 17C, 283, 17C, ... If anyone has any idea of what else to try, it would be much appreciated!
Fitter cannot ...
I am trying to set up a basic SDI transmitter on an Agilex 5. Currently, my setup is a 148.5 MHz refclk, a GTS PMA Direct PHY IP configured for 12G SDI, a GTS Reset Sequencer, and a GTS System PLL configured to take in the refclk and output 742.5 MHz (this is based on the minimum system PLL frequency recommendation in the SDI II IP documentation). I have my serial output differential pair on pins BE129 and BE126 which are the GTS Left 1B TX 0 channels, and my refclk coming in as a differential pair on pins AY120 and AY115 which are the refclk pins for GTS Left 1B. According to the documentation for the SoM, these refclk pins should be configured to 148.5 MHz. For some reason, when I try to compile, the fitter fails in the plan stage with error 14566 "The Fitter cannot place 1 periphery component due to conflicts with existing constraints (1 I/O pad). Fix the errors described in the submessages, and then rerun the Fitter." The submessages read, "Illegal constraint of I/O pad to the location PIN_AY115" (175019), "No legal location could be found out of 1 considered location. Reasons why each location could not be used are summarized below:" (16234), "There is no routing connectivity between the I/O pad and the destination I/O input buffer" (175006), "The I/O pad could not be placed in any location to satisfy its connectivity requirements" (175022), and "The destination I/O input buffer could not be placed in any location to satisfy its connectivity requirements" (175022). There isn't very much logic surrounding the system (basically just a counter to create some dummy input data), so I'm not sure why it wouldn't be able to connect specifically the n side of the refclk. Has anyone encountered similar issues/errors and could maybe point me in the right direction? Any help would be appreciated.
