Agilex™ 7 I-Series FPGA Transceiver SoC Development Kit GSRD Build
I am attempting to build the GSRD using the Intel® Agilex™ 7 I-Series FPGA Transceiver SoC Development Kit (4x F-Tile) DK-SI-AGI027FA. Quartus Version: 24.3.1 Reference Document: https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/i-series/soc/gsrd/ug-gsrd-agx7i-soc/ When running the "Build Hardware Design" procedure according to the instructions: make BOARD_TYPE=devkit_fm87 BOARD_PWRMGT=linear QUARTUS_DEVICE=AGIB027R31B1E1V ENABLE_HPS_EMIF_ECC=1 FPGA_SGPIO_EN=1 HPS_F2S_IRQ_EN=1 generate_from_tcl all It throws the following log error and fails to proceed: make[1]: *** [Makefile:817: qsys_generate_qsys] Error 1 make[1]: Leaving directory '/home/nict/p.agilex7_gsrd/gsrd.dk_si_agi027fa/agilex_soc_devkit_ghrd' make: *** [Makefile:833: generate_from_tcl] Error 2 Could you please advise what might be causing this issue, or let me know which logs (such as QSYS/Platform Designer logs) I should check?
IO Standard for GTS Transceiver REFCLK
Hi, We use on the Agilex 5 and 3 Transceivers with AC coupling. Agilex 5 requires CML, HCSL in Agilex 5 datasheet. However, Agilex 5 Premium kit uses LVDS Clock for some Transceiver REFCLK. Is it possible to use LVDS as REFCLK for XCVRs when we use with AC Coupling ?
AXI4-Lite Firewall IP core - Altera support request
Greetings Altera, Just FYI, I writing in the community forum, in addition to a sent an inquiry yesterday, through the website contacts form - https://www.altera.com/contact - in attempt to get into contact and start a conversation going with some of your FAEs regarding a problem our company and team is facing: Currently in one of our FPGA Designs utilizing Altera FPGAs (CycloneV SoC ARM (5CSEBA5)), there is a requirement to monitor and control data streams/transfers between AXI4 master and slave devices. We have to ensure those are occurring in the allowed (configurable) address ranges, and if not, such data transfer is canceled – both downstream and upstream, the master is kept aware, and an interrupt is driven out. A Nios II CPU shall be able to configure (access) this IP core – set these address ranges, read statuses, etc. Also it will be the recipient of the IRQ from core in case of faults. Basically, we are looking for a simple configurable (read&write) AXI4-Lite Firewall/Pass-through/Configurable Bridge (whatever you want to call it) type of IP core – that will sit between two AXI connected type devices (master on one-side & slave on the other) and oversee the communication between them. For Altera Cyclone V SoC FPGAs. At this point we cannot find such component from the Altera’s Quartus IP cores (Platform Designer) library. Also, it is not obvious for us how to, or, even if it is possible to ‘construct’ such device, from other IPs already available in the library ??? That’s why I am reaching to you for support on the matter. To check what approach or solution can you suggest , do you have anything available as service or ip core that could solve our problem, recommend us an IP vendor , etc... Here's a general block diagram of what we have in mind: (download the attached .png for better resolution) I hope we can talk soon. Best Regards, - Georgi M.LVDS Output of FPGA
Hi all, I am using Arria 10 FPGA part number: 10AX066N2F40E1HG for one of my projects. There is a clock output from FPGA that goes to an external chip. This clock is configured as LVDS. Currently debugging an issue, and focused on enhancing the signal quality at the output of the FPGA. The output signal we measure in scope is not as good as we would expect. We expect a step signal, but the testing output shows a triangular signal! I have the following questions. 1) Is there settings/knobs I could tweak in my LVDS IP, or any other ideas to improve output signal quality? ( I learned about pre_emphasis setting), But other ideas could help. 2) Is there an inbuilt tool within FPGA to check the eye diagram or measure the output signal quality?instead of relying on an oscilloscope?. Note: I am using Quartus 2018 standard version. Let me know if you need further information. Thankyou.
DDR2 license Question
The customer obtained the DDR2 license through the Altera website. Does this IP license have any time limitation or other usage restrictions? When generating the project for the EP4CE75U19I7N device, Quartus only generates project.sof and does not generate project_time_limited.sof.
Cascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packets
Hello community, I have a DSP system with 32 independent 256-bit output channels using Avalon-ST (or AXI-Stream) on an AGX FPGA. To transfer packetized data to the HPS, I implemented a cascaded Avalon Streaming Multiplexer architecture. The 32 channels are divided into two groups of 16. Each group connects to a 16-to-1 Avalon-ST Multiplexer IP. The outputs of these two multiplexers are then connected to a final 2-to-1 Avalon-ST Multiplexer IP, forming an overall 32-to-1 mux structure. At the output of the final 2-to-1 mux, I also added another 2-to-1 Avalon-ST mux with a selectable input for a data packet emulator. Using the emulator path, I verified that the FPGA-to-HPS data path is functioning correctly. However, after switching from the emulator path to the DSP output path, I only receive packets from channel 0. No packets from the other DSP channels are observed by the HPS. For debugging, I intentionally generated valid packets on non-zero channels. In SignalTap, I observed that channel 28 was asserting valid packet data (valid = 1) while ready = 0. This capture was taken at the input of the second 16-to-1 mux, since channel 28 belongs to the upper 16-channel group. Next, I changed the SignalTap trigger condition to the rising edge of the output valid signal of the second 16-to-1 mux. However, the trigger condition was never met, even after repeated acquisitions. The ready signals throughout the mux stages remain asserted, which suggests there is no downstream backpressure from the FIFO path to HPS. The downstream FIFO status also indicates that it is empty. The confusing part is the following: After enabling channel 0 again, both channel 0 and channel 28 should have had valid packets simultaneously. In this case, packets from channel 0 were forwarded correctly to the HPS. I verified this by reading 8 words from the memory FIFO and reconstructing the original packet; all received packets contained the channel ID corresponding to channel 0. However, after disabling channel 0 again, no new packets were received from any channel, including channel 28. Based on these observations, it appears that the internal round-robin scheduler of the Avalon-ST mux may not be operating correctly. The two 16-to-1 muxes and the final 2-to-1 mux are all configured identically in Platform Designer. Does anyone have suggestions on what could cause this issue, or recommendations on how to further debug the Avalon-ST mux behavior? I noticed an interesting behavior on channel 28 related to the Avalon-ST handshake. The ready signal for channel 28 remains asserted during idle cycles, but it becomes deasserted exactly when valid is asserted. In other words: | Cycle | valid | ready | | ---------- | ----- | ----- | | Idle | 0 | 1 | | Data cycle | 1 | 0 | | Next cycle | 0 | 1 | This differs from channel 0, where both valid and ready are asserted simultaneously, forming a successful Avalon-ST handshake. My DSP source currently only pulses `valid` for one cycle when data is available. Could the Avalon-ST Multiplexer scheduling size setting (Scheduling Size = 2) contribute to this behavior? Specifically, can the mux arbitration latency caused by the scheduling configuration prevent non-zero channels from completing a handshake if valid is only asserted for one cycle? Thank you very much.
GTS Transceiver Simulation Model Encrypted file - unable to decrypt with Cadence Xcelium
Hi everyone, I am working on integrating the generated simulation models of the Agilex-5 GTS PMA/FEC Direct PHY IP with our main IP. I have encountered an issue where an encrypted file within the models cannot be decrypted by the Cadence Xcelium Simulator. The file is located at: <ip>/n_channel_superset_2100/sim/intelfpga/intel_src_flow_ctrl.sv I have tested this with Cadence Xcelium versions 19.x, 20.x, and 22.x, but the decryption error persists across all versions. We are currently using Quartus Pro Edition 2026.1.0 with an evaluation license. Could you please provide guidance on how to resolve this decryption issue? Thanks, ArunAvalon Transaction Responses & Bridges
Hello I have a question about the behavior of Avalon-MM Pipeline Bridges concerning the response signals. I have the following setup: 2 (or more) Avalon-MM Masters Master cmd_ctrl (supports Avalon responses) Master B (no response support) global_mm_bridge (pipeline Bridge IP Core) with Support for Transaction Responses Multiple Slaves Slave global_reg (simple register read & write access) other Slaves do not have Avalon response signals (neither readdatavalid, nor writeresponsevalid) My understanding of Avalon-MM bridges was always that they act as kind of "transparent bridge", i.e. they do not sent responses by themselves, but only transfer/route the responses of the addressed slave behind the bridge. However, when I capture the transactions using Signaltap I noticed that the Bridge is creating a writerepsonse valid before, this is even processed by the addressed slave. In the signaltap capture, you can see the writereponse (highlighted in yellow) arriving at the initiating master (cmd_ctrl) before, the addressed slave (global_reg) even generates it. Hence I would assume this is generated by the mm_bridge directly after it accepts the write command. Now my questions are: Is this the intended behavior of a pipeline bridge? If yes, is there any way to modify the settings of the bridge, to make sure the master (cmd_ctrl) only receives a writeresponsevalid after the respective slave has sent it? Background is: cmd_ctrl also needs to write/read from slave B, however this must not be done, before the slave global_reg has fully processed the write command, as it must prepare some glue logic. Is there any other option to realize a fully transparent Avalon-MM bridge? best regards Fabian
