ContributorCorrect way to configure the RGMII input and output pins on a MAX10 FPGA
Greetings ALTERA Expetrs,
I am using an ALTERA Triple Speed Ethernet IP core configured n MAC only mode, which talks to a MARVELL 88E1111 PHY. Actually for this example i am using an ALTERA MAX10 10M50-C Development kit. I am having trouble understanding exactly HOW to configure the DDR RGMII input and output pins.
After instantiating the Triple Speed Ethernet IP in a top level System Verilog file and connecting up Avalon MM, Avalon Tx/Rx ST interfaces etc, and connecting up clocks and resets, do i need to to connect up my RGMII DDR outputs using altddio_out IP and my RGMII DDR inputs to FPGSA pins using altddio_in IP blocks ?
This is how i am thinking i need to connect my DDR RGMII FPGA pins up to my Triple Speed Ethernet RGMII tx in and rx in busses on the IP:
Connect the TX Clock output :
altddio_out #(.width(1), .INTENDED_DEVICE_FAMILY("max10"))
altddio_out_a_txc (.outclock (clk_125MHz),
.datain_h (1'b1),
.datain_l (1'b0),.dataout (RGMII_ETH_TXC), // TSE clock TX PORT A
.oe (1'b1),
.outclocken (1'b1),
.aclr (1'b0),
.aset (1'b0)
);
Connect the RGMI TX data outputs :
altddio_out #(
.width(4),
.INTENDED_DEVICE_FAMILY("max10")
) altddio_out_a_txd (
.outclock (clk_125MHz), // 125 MHz Transmit clock for RGMII
.datain_h (rgmii_out_ddr), // rising edge
.datain_l (rgmii_out_ddr), // falling edge
.dataout (rgmii_out),
.aclr (1'b0),
.aset (1'b0),
.oe (1'b1),
.outclocken (1'b1)
);
Where in the above code rgmii_out wires are going to FPGA DDR RGMI TX output pins, and rgmii_out_ddr is from the Triple speed IP core.
For the RX side for the INPUT DDR RGIM Rx data bus:
altddio_in #(.width(4), .INTENDED_DEVICE_FAMILY("max10")) altddio_in_a_rxd (
.inclock (RGMII_ETH_RXC),
.datain (rgmii_in),
.dataout_h (rgmii_rxd),
.dataout_l (/* unused */)
);
Do these sort of DDR interface IP instantiations looks correct ?
All help gratefully received !
Thanks, Dr Barry H
