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drbarryh's avatar
drbarryh
Icon for Contributor rankContributor
6 months ago

Correct way to configure the RGMII input and output pins on a MAX10 FPGA

Greetings ALTERA Expetrs, I am using an ALTERA Triple Speed Ethernet IP core configured n MAC only mode, which talks to a MARVELL 88E1111 PHY. Actually for this example i am using an ALTERA MAX10 10...
Ethernet
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
6 months ago

Hi Barry,
not sure why you're instantiating dedicated DDR IO. TSE IP in RGMII mode already interfaces to DDR RX and TX data.


Regards
Frank