Correct way to configure the RGMII input and output pins on a MAX10 FPGA

Hi Frank, thanks for your reply. Yes i figured that out with the error messages i received from Quartus after i tried instantiating my own DDR I/Os ! The error message was saying that the TSE already instanced some GPIO Lite DDR I/Os (the MAX10 equivalent). I just am not that familiar with the MAX10 FPGA's or the TSE, and just getting back into Quartus as well after many years using Vivado and Xilinx FPGAs !

But i am getting better gradually !

Now i have managed to reconstruct the ALTERA MAX 10 example design using the following approach :

Create a new project -> use the par file: max10tse_q_18_0_std.par from the MAX10 TSE Example design, in Quartus 2018 it fails to reconstruct the Qsys platform because of a lot of missing IPs (like the packet gen, packet mon etc.). But then i tried it from the  max10tse_q_17_0_std.par version, then tried to do an update to Quartus 2018 and luckily that works and gets me all the missing Qsys IPs. 

I then tried to compile that project in Quartus 2018 and hey presto it compiled ok and met timing! Great progress i thought ! I connected a Windows 10 PC to my dev kit using an Ethernet cable and programmed in its MAC address as the DST address for the Tests. Also tried the same tests using a UBUNTU PC. But i get the same failed results at the moment.

But when i try out the TCL scripts in the sc_tcl sub directory and run them, the TEST_MAC_LB "1000M" and  TEST_MAC_PHY_LB "1000M" commands both fail, after i of course run the source main.tcl script.
I am using a ALTERA MAX10 10M50-C dev kit as my base for these tests. In the stats_chk command results i see all frames transmitted (100000) but 0 frames are being received.

Any ideas on what is still going wrong and a solution would be most appreciated ! I am stuck now :)

Thanks, Dr Barry H