Agilex 7 I F-Tile Direct PHY: example TB doesn't work

Question

Hello community,I'm unable to run an example design for F-Tile on Agilex 7 I-Series device.I've tried following:1. generate an example design using platform designer,2. open the generated project using quartus and click Support-Logic Generation,3. Tools -&gt; Generate Simulator Setup Script for IP, select output directory "sim" inside the generated project,4. Using QuestaSim go into freshly generated "sim/mentor" folder and put:&nbsp;do run_msim_setup.tclset TOP_LEVEL_NAME top_tstelab_debugadd waves for u0, u1 instances,5. run 2 ms (100 us will do it too)6. See that the rx_ready doesn't go up (but tx_ready does).Used tools:Quartus: 26.1 proQuestaSim: 2023.4, 2025.3, 2026.1OS: Debian 13, Windows 11.What could lead to such behavior? Is there something could be done differently? Any ideas?Best regards.

ash_r_intel · Answer

Hi,
For the generated example designs, the scripts are already created. You just need to navigate to the right directory and source the scripts in the terminal. Make sure that the Quartus and the simulator are correctly loaded. For reference, go through the last portion of the following section in the user guide.
https://docs.altera.com/r/docs/683872/25.3/f-tile-architecture-and-pma-and-fec-direct-phy-ip-user-guide/example-design-generation.
&nbsp;
Regards

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Agilex 7 I F-Tile Direct PHY: example TB doesn't work

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Agilex 7 I F-Tile Direct PHY: example TB doesn't work