Forum Discussion
New ContributorAgilex 7 I F-Tile Direct PHY: example TB doesn't work
Hello community,
I'm unable to run an example design for F-Tile on Agilex 7 I-Series device.
I've tried following:
1. generate an example design using platform designer,
2. open the generated project using quartus and click Support-Logic Generation,
3. Tools -> Generate Simulator Setup Script for IP, select output directory "sim" inside the generated project,
4. Using QuestaSim go into freshly generated "sim/mentor" folder and put:
do run_msim_setup.tcl
set TOP_LEVEL_NAME top_tst
elab_debug
add waves for u0, u1 instances,
5. run 2 ms (100 us will do it too)
6. See that the rx_ready doesn't go up (but tx_ready does).
Used tools:
Quartus: 26.1 pro
QuestaSim: 2023.4, 2025.3, 2026.1
OS: Debian 13, Windows 11.
What could lead to such behavior? Is there something could be done differently? Any ideas?
Best regards.
Hi,
For the generated example designs, the scripts are already created. You just need to navigate to the right directory and source the scripts in the terminal. Make sure that the Quartus and the simulator are correctly loaded. For reference, go through the last portion of the following section in the user guide.
Regards
3 Replies
Ash_R_AlteraRegular Contributor
Hi,
For the generated example designs, the scripts are already created. You just need to navigate to the right directory and source the scripts in the terminal. Make sure that the Quartus and the simulator are correctly loaded. For reference, go through the last portion of the following section in the user guide.
Regards
- Ash_R_Altera
Please let me know if further assistance is needed or if the solution worked for you.
Regards
kharitonowThanks for response.
It works using example_design/testbench/run_vsim.tcl script.
The only differences I see between my approach in the simulation startup and the generated script-basted startup script lies in defines, which are placed in USER_DEFINED_COMPILE_OPTIONS and USER_DEFINED_VERILOG_COMPILE_OPTIONS variables.
