Agilex 7 R-Tile PCIe Gen5: Avalon-ST DMA MWr TLP accepted by HIP but never received by Root Port

I am debugging a design using the Intel mSGDMA Read Master IP connected to the Intel Agilex 7 R-Tile PCIe Gen5 Hard IP through the Avalon-ST TX interface.The design uses the Intel mSGDMA Read Master to read data from memory. The Avalon-MM read data is then packetized into PCIe Memory Write (MWr) TLPs and transmitted through the R-Tile PCIe HIP. The transmit path is:

Intel mSGDMA Read Master → dma_mwr_txc_gen → txc_mux_2to1 → pcie_bam_avst_intf → pcie_pio → Agilex 7 R-Tile PCIe HIP

The endpoint enumerates correctly, the PCIe link trains successfully to Gen5 x16, configuration space accesses work correctly, BAR accesses work correctly, and normal MMIO/PIO operations function as expected. The only issue occurs when transmitting DMA-generated Memory Write TLPs.

We have spent considerable time verifying the transmit path using both simulation and Signal Tap, and everything appears to be correct up to the HIP interface. Specifically, we have verified the following:

• The Avalon-ST TX interface follows the R-Tile User Guide.
• SOP/EOP placement is correct.
• Segment valid signals are correct.
• Header valid and payload valid are correct.
• ready remains asserted throughout the transfer.
• No Avalon-ST protocol violations are observed.
• The ACC signal gets asserted after the TLP is sent to the HIP

The generated Memory Write header decodes correctly (128-byte MWr, correct addresses, requester ID, and length field). Payload contents are correct. Address increments correctly between successive packets. Signal Tap shows the expected TLP immediately before entering the HIP. The HIP accepts the packet (valid and ready handshake completes). No HIP or protocol error indications are observed.

However, the Root Port never appears to receive the Memory Write TLP. The expected data never becomes visible to the host software, even though the packet appears to have been accepted by the HIP.

After several DMA attempts, the Root Port—or sometimes the entire server—eventually becomes unresponsive and requires a reboot. We do not observe any AER messages, completion timeout messages, or other PCIe errors reported by the operating system. We also investigated timing closure to rule out timing-related corruption. 

At this point, we are trying to determine whether there is something beyond the Avalon-ST interface that could cause the HIP to silently discard or otherwise fail to transmit a posted Memory Write TLP.

Has anyone encountered a similar issue on the Agilex R-Tile PCIe HIP where:

the Avalon-ST interface appears completely correct, the HIP accepts the packet (ready/valid handshake completes), no protocol or PCIe errors are reported, but the Root Port never receives the posted Memory Write?

Are there any additional HIP status registers, debug signals, credit counters, packet validation checks, alignment requirements, or other R-Tile-specific conditions that should be examined? Are there any known situations where a posted Memory Write can be silently drop after being accepted on the Avalon-ST interface?

Any suggestions on additional debug points or known R-Tile HIP behaviors would be greatly appreciated.

Thank you.
Reza