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Reza_Fidus_ASAP
New Contributor
New ContributorAgilex 7 R-Tile PCIe Gen5: Avalon-ST DMA MWr TLP accepted by HIP but never received by Root Port
I am debugging a design using the Intel mSGDMA Read Master IP connected to the Intel Agilex 7 R-Tile PCIe Gen5 Hard IP through the Avalon-ST TX interface.The design uses the Intel mSGDMA Read Master ...
RongY_altera
Contributor
ContributorHi Reza,
If the RP is a CPU-based server, you'll needs to allocate a mem space for FPGA to write to. The mem space will have a virtual address range. Your MWr should write to that address.
Regards,
Rong
