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New ContributorWhy the Error Response Slave IP cannot work for Agilex 5 SOC FPGA?
I test the GHRD and corresponding linux image on Terasic DE25-Nano board， however, when I access the FPGA peripheral device, like SW, I use md.l 0x20010060 1 command in U-Boot console, it reports the register value; when I use md.l 0x2fffffff 1 (the H2F ummapped address) or md.l 0x4fffffff 1 (the LWH2F ummapped address), the system will hang up, report Please reset the board!
then I added a Error Response Slave IP and tested, but it still report the same message, then, I need reboot my system every time.
I set the IP as follows:
after this, I added two Error Response Slave IPs in the system, one is for H2F, another is for LWH2F:
Unfortunately, the problem still remains unsolved.
1 Reply
tehjingy_AlteraRegular Contributor
Hi DLiu5
This is an expected behavior.
Accessing an undefined memory space in the U-boot will cause a Segmentation Fault and a reset is required to resolve the issue.
As for your question on the Error Response Slave IP. The IP will not stop any read/write to undefined memories.
The IP will only trigger an interrupt when an undefined read had occurred and the user will need to react to the undefined transaction.
You could find out more on how the IP reports the error here:
Regards
tehjingy
