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DLiu5's avatar
DLiu5
Icon for New Contributor rankNew Contributor
3 months ago

Why the Error Response Slave IP cannot work for Agilex 5 SOC FPGA?

I test the GHRD and corresponding linux image on Terasic DE25-Nano board， however, when I access the FPGA  peripheral device, like SW, I use md.l 0x20010060 1 command in U-Boot console, it reports th...
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tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 months ago

Hi DLiu5 

 

This is an expected behavior.

Accessing an undefined memory space in the U-boot will cause a Segmentation Fault and a reset is required to resolve the issue.

 

As for your question on the Error Response Slave IP. The IP will not stop any read/write to undefined memories.

The IP will only trigger an interrupt when an undefined read had occurred and the user will need to react to the undefined transaction.

You could find out more on how the IP reports the error here:

https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide/error-response-slave-access-violation-service

 

 

 

Regards

tehjingy