drbarryh
Contributor
ContributorConfusion for TX Clock direction for Triple Speed 1G Ethernet IP?
Hello ALTRA IP experts,
Can anybody please explain to me why, when i set the Triple Speed Ethernet IP up for RGMII mode, the tx clock for the MAC is set as an input?
eth_tse_0_pcs_mac_tx_clock_clk : in std_logic := 'X'; -- clk
I was expecting this signal to be an output for the Transmit MAC section to to the PHY TX block ?
Here are all of the signal connections i get when i setup in RMII mode for the Triple Speed 10/100/1000 Ethernet IP core (its easier to see directions and sizes using the VHDL instance template) :
eth_tse_0_mac_status_set_10 : in std_logic := 'X'; -- set_10
eth_tse_0_mac_status_set_1000 : in std_logic := 'X'; -- set_1000
eth_tse_0_mac_status_eth_mode : out std_logic; -- eth_mode
eth_tse_0_mac_status_ena_10 : out std_logic; -- ena_10
eth_tse_0_mac_rgmii_rgmii_in : in std_logic_vector(3 downto 0) := (others => 'X'); -- rgmii_in
eth_tse_0_mac_rgmii_rgmii_out : out std_logic_vector(3 downto 0); -- rgmii_out
eth_tse_0_mac_rgmii_rx_control : in std_logic := 'X'; -- rx_control
eth_tse_0_mac_rgmii_tx_control : out std_logic; -- tx_control
eth_tse_0_receive_data : out std_logic_vector(31 downto 0); -- data
eth_tse_0_receive_endofpacket : out std_logic; -- endofpacket
eth_tse_0_receive_error : out std_logic_vector(5 downto 0); -- error
eth_tse_0_receive_empty : out std_logic_vector(1 downto 0); -- empty
eth_tse_0_receive_ready : in std_logic := 'X'; -- ready
eth_tse_0_receive_startofpacket : out std_logic; -- startofpacket
eth_tse_0_receive_valid : out std_logic; -- valid
eth_tse_0_transmit_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
eth_tse_0_transmit_endofpacket : in std_logic := 'X'; -- endofpacket
eth_tse_0_transmit_error : in std_logic := 'X'; -- error
eth_tse_0_transmit_empty : in std_logic_vector(1 downto 0) := (others => 'X'); -- empty
eth_tse_0_transmit_ready : out std_logic; -- ready
eth_tse_0_transmit_startofpacket : in std_logic := 'X'; -- startofpacket
eth_tse_0_transmit_valid : in std_logic := 'X'; -- valid
eth_tse_0_mac_mdio_mdc : out std_logic; -- mdc
eth_tse_0_mac_mdio_mdio_in : in std_logic := 'X'; -- mdio_in
eth_tse_0_mac_mdio_mdio_out : out std_logic; -- mdio_out
eth_tse_0_mac_mdio_mdio_oen : out std_logic; -- mdio_oen
eth_tse_0_mac_misc_magic_wakeup : out std_logic; -- magic_wakeup
eth_tse_0_mac_misc_magic_sleep_n : in std_logic := 'X'; -- magic_sleep_n
eth_tse_0_mac_misc_ff_tx_crc_fwd : in std_logic := 'X'; -- ff_tx_crc_fwd
eth_tse_0_mac_misc_ff_tx_septy : out std_logic; -- ff_tx_septy
eth_tse_0_mac_misc_tx_ff_uflow : out std_logic; -- tx_ff_uflow
eth_tse_0_mac_misc_ff_tx_a_full : out std_logic; -- ff_tx_a_full
eth_tse_0_mac_misc_ff_tx_a_empty : out std_logic; -- ff_tx_a_empty
eth_tse_0_mac_misc_rx_err_stat : out std_logic_vector(17 downto 0); -- rx_err_stat
eth_tse_0_mac_misc_rx_frm_type : out std_logic_vector(3 downto 0); -- rx_frm_type
eth_tse_0_mac_misc_ff_rx_dsav : out std_logic; -- ff_rx_dsav
eth_tse_0_mac_misc_ff_rx_a_full : out std_logic; -- ff_rx_a_full
eth_tse_0_mac_misc_ff_rx_a_empty : out std_logic; -- ff_rx_a_empty
clk_out_5_clk : out std_logic; -- clk
eth_tse_0_pcs_mac_tx_clock_clk : in std_logic := 'X'; -- clk
eth_tse_0_pcs_mac_rx_clock_clk : in std_logic := 'X'; -- clk
eth_tse_0_mac_clkena_rx_clkena : in std_logic := 'X'; -- rx_clkena
eth_tse_0_mac_clkena_tx_clkena : in std_logic := 'X' -- tx_clkena
These all make sense to me EXCEPT for the eth_tse_0_pcs_mac_tx_clock_clk signal which i thought would be an OUPUT and NOT and INPUT !
Thanks for your help,
Barry
