Confusion for TX Clock direction for Triple Speed 1G Ethernet IP?

Greetings Pavee, Thanks for your reply.

But that is incorrect for my application. Looking for example at an ALTERA MAX10 10M50-C development kit, which has a pair of Triple Speed Ethernet connections, and using a MARVELL 88E1111 PHY, on page 53 of the MARVELL Data sheet it is clearly shown in RGMII mode that the Tx clock is an INPUT to the MARVELL PHY device (TXC, going to GTX_CLK in the PHY), and an OUTPUT from the MAC (which is inside the MAX10 FPGA in this case) and so the so the Tx clock is coming from the ALTERA Triple Speed IP core instantiated and configured in MAC only mode..

I am not sure if this is the usual case but it certainly is in this case.

Best regards,

Dr Barry H