QPP 26.1 fails to generate PLL IP

Hello,

I'm unable to generate a simple PLL IP on a particular Win 11 machine.  It works fine on a different Win 11 machine.  Below is a partial log that shows the error.    Note that I replaced my own user name with <username> below.   

Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\Projects\fw_ml_module_local\ip\pll_io.ip --synthesis=VERILOG --output-directory=C:\Projects\fw_ml_module_local\ip\pll_io --family="Agilex 3" --part=A3CY050BB18AI6S
Info: pll_io.iopll_0: Able to implement PLL with user settings
Info: pll_io: "Transforming system: pll_io"
Info: pll_io: "Naming system components in system: pll_io"
Info: pll_io: "Processing generation queue"
Info: pll_io: "Generating: pll_io"
Info: pll_io: "Generating: pll_io_altera_iopll_2110_txusefy"
Error: add_fileset_file: No such file C:/altera_pro/26.1/ip/altera/altera_iopll/top/{C:/Users/<username>/AppData/Local/Temp/alt0637_15290807326924327962.dir/0003_iopll_0_gen/altera_falconmesa_ph2_iopll.sdc}
while executing
"add_fileset_file ${output_name}.sdc SDC_ENTITY PATH $sdc_file {NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION READ_DURING_POST_SYN_AND_POST_FIT_TIMING_AN..."
(procedure "generate_sdc_related_files" line 560)
invoked from within
"generate_sdc_related_files $tmpdir $name "
(procedure "generate_sdcs_and_mif" line 24)
invoked from within
"generate_sdcs_and_mif $name"
(procedure "generate_synth_falconmesa_ph2" line 12)
invoked from within
"generate_synth_falconmesa_ph2 $name"
(procedure "generate_synth" line 9)
invoked from within
"generate_synth pll_io_altera_iopll_2110_txusefy"
Info: pll_io: Done "pll_io" with 2 modules, 4 files
Info: Finished: Create HDL design files for synthesis
Info: Generation of C:/Projects/fw_ml_module_local/ip/pll_io.ip (pll_io) took 9192 ms

When I run the same PLL generation on a different Win 11 machine, I don't see mention of add_fileset_file in the log.   

Below are the Generation settings.