Confusion for TX Clock direction for Triple Speed 1G Ethernet IP?

In RGMII, the MAC does not generate its own transmit clock.
Instead, the PHY is responsible for supplying the 125/25/2.5 MHz TX clock back to the MAC.

So, MAC sends TX data (txd and tx_ctl) to the PHY. The PHY returns a clock  that is aligned with the transmitted data. The MAC uses this returned clock to output the next cycle of data. Hence, This is correct for RGMII as an input signal.

Hope this helps.