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drbarryh
Contributor
ContributorConfusion for TX Clock direction for Triple Speed 1G Ethernet IP?
Hello ALTRA IP experts, Can anybody please explain to me why, when i set the Triple Speed Ethernet IP up for RGMII mode, the tx clock for the MAC is set as an input? eth_tse_0_pcs_mac_tx_clock_clk ...
FvM
Super Contributor
Super ContributorHi Barry,
according to TSE IP User Guide, interface between FPGA and RGMII PHY looks like this
means 5/25/125 MHz clock has to be generated in your design. That's valid for all PHY with RGMII interface, not specifically Marvell 88E1111.
Regards
Frank
