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drbarryh's avatar
drbarryh
Icon for Contributor rankContributor
7 months ago

Confusion for TX Clock direction for Triple Speed 1G Ethernet IP?

Hello ALTRA IP experts, Can anybody please explain to me why, when i set the Triple Speed Ethernet IP up for RGMII mode, the tx clock for the MAC is set as an input? eth_tse_0_pcs_mac_tx_clock_clk ...
Ethernet
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
6 months ago

Hi Barry,
according to TSE IP User Guide, tx_clk has to be send to RGMII PHY and TSE IP by your design. A programmable clock divider is required to support 10 and 100 MBit mode.

 


Regards
Frank