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ContributorLVDS Output of FPGA
Hi all,
I am using Arria 10 FPGA part number: 10AX066N2F40E1HG for one of my projects.
There is a clock output from FPGA that goes to an external chip. This clock is configured as LVDS. Currently debugging an issue, and focused on enhancing the signal quality at the output of the FPGA. The output signal we measure in scope is not as good as we would expect. We expect a step signal, but the testing output shows a triangular signal!
I have the following questions.
1) Is there settings/knobs I could tweak in my LVDS IP, or any other ideas to improve output signal quality? ( I learned about pre_emphasis setting), But other ideas could help.
2) Is there an inbuilt tool within FPGA to check the eye diagram or measure the output signal quality?instead of relying on an oscilloscope?.
Note: I am using Quartus 2018 standard version. Let me know if you need further information.
Thankyou.
6 Replies
AqidAyman_AlteraRegular Contributor
Hi,
My suggestion is to first try the FPGA-side knobs that are actually available for Arria 10 LVDS TX: pre-emphasis and VOD, then quickly validate whether the triangular shape is really a transmitter issue or instead caused by termination, channel loss, or probing setup. For actual eye-diagram verification of the LVDS output on board, an oscilloscope or SI simulation is still the right method; Arria 10 does not provide a built-in on-chip analog eye monitor for standard LVDS output pins.
MK_ABQHi,
Thank you. I will try the two knobs. Apart from pre-emphasis and VOD, what other knobs are available for LVDS TX? I was thinking the following.
slew rate, current strength, weak pull up? any of these?
- MK_ABQ
Hi AqidAyman_Altera ,
I see an option to tweak I/O delay. This will be very useful for me. my FPGA OPN is 10AX066N2F40E1HG. I am trying to find which setting from the following table applies to my FPGA, and it's confusing.
Does my FPGA LVDS serdes I/O belong to slow model (E1H) highlighted part? or Fast Model Extended?
- AqidAyman_Altera
It depends on your design. You can refer to both. Both models refer to process corner models used in timing analysis which the slow model represents worst-case process/voltage/temperature and the fast model represents best-case.
These are not encoded in the OPN suffix directly; they are timing analysis corners applied to your speed grade.
Reference: https://docs.altera.com/r/docs/683243/25.3/quartus-prime-pro-edition-user-guide-timing-analyzer/multicorner-timing-analysis
FvMSuper Contributor
Hi,
observing "triangle" (slow rise/fall time) waveform suggests that you are no terminating LVDS outputs correctly. To see expected waveform according to LVDS standard, output need to be terminated with 100 ohm differential respectively 50 ohm single ended. Expect trf of e.g. 0.3 ns with correct termination.
Regards Frank
