LVDS Output of FPGA

Hi all,

I am using Arria 10 FPGA part number: 10AX066N2F40E1HG for one of my projects.

There is a clock output from FPGA that goes to an external chip. This clock is configured as LVDS. Currently debugging an issue, and focused on enhancing the signal quality at the output of the FPGA. The output signal we measure in scope is not as good as we would expect. We expect a step signal, but the testing output shows a triangular signal!

I have the following questions.

1) Is there settings/knobs I could tweak in my LVDS IP, or any other ideas to improve output signal quality? ( I learned about pre_emphasis setting), But other ideas could help.

2) Is there an inbuilt tool within FPGA to check the eye diagram or measure the output signal quality?instead of relying on an oscilloscope?.

Note: I am using Quartus 2018 standard version. Let me know if you need further information.

Thankyou.