Forum Discussion
MK_ABQ
Contributor
ContributorLVDS Output of FPGA
Hi all, I am using Arria 10 FPGA part number: 10AX066N2F40E1HG for one of my projects. There is a clock output from FPGA that goes to an external chip. This clock is configured as LVDS. Currently d...
AqidAyman_Altera
Regular Contributor
Regular ContributorHi,
My suggestion is to first try the FPGA-side knobs that are actually available for Arria 10 LVDS TX: pre-emphasis and VOD, then quickly validate whether the triangular shape is really a transmitter issue or instead caused by termination, channel loss, or probing setup. For actual eye-diagram verification of the LVDS output on board, an oscilloscope or SI simulation is still the right method; Arria 10 does not provide a built-in on-chip analog eye monitor for standard LVDS output pins.
