Forum Discussion
ContributorLVDS Output of FPGA
ContributorHi AqidAyman_Altera ,
I see an option to tweak I/O delay. This will be very useful for me. my FPGA OPN is 10AX066N2F40E1HG. I am trying to find which setting from the following table applies to my FPGA, and it's confusing.
Does my FPGA LVDS serdes I/O belong to slow model (E1H) highlighted part? or Fast Model Extended?
Regular ContributorIt depends on your design. You can refer to both. Both models refer to process corner models used in timing analysis which the slow model represents worst-case process/voltage/temperature and the fast model represents best-case.
These are not encoded in the OPN suffix directly; they are timing analysis corners applied to your speed grade.
Reference: https://docs.altera.com/r/docs/683243/25.3/quartus-prime-pro-edition-user-guide-timing-analyzer/multicorner-timing-analysis
- AqidAyman_Altera
