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dc3's avatar
dc3
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29 days ago

Can't generate F-Tile Ethernet Hard IP Design Example

When I try to generate an example design for the F-Tile Ethernet Hard IP or even the F-Tile Low Latency 100G Ethernet IP, the generating step gets stuck in a loop and will stay that way until I manua...
Ethernet
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
22 days ago

Hello,

 

May I know which Quartus version you're working with? Do the issue still persist?

 

Regards,

Pavee

  • dc3's avatar
    dc3
    Icon for New Contributor rankNew Contributor
    14 days ago

    I upgraded to 25.3.1 and now I get this error.

     

    • paveetirrasrie_Altera's avatar
      paveetirrasrie_Altera
      Icon for Frequent Contributor rankFrequent Contributor
      2 days ago

      Hello,

       

      Form the screenshot you've provided, the design has error. You won't be able to generate the design with error.

      Please select the valid Device Initialization Clock and continue with generation.

       

      Regards,

      Pavee