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MichaelL's avatar
MichaelL
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4 months ago

Behavior of 10 GX Avalon-MM Interface for PCI Express* IP Core when byteenable=16'h0000

Hi, we are using an Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* IP Core. During our tests we noticed some illegal PCIe packages generated presumable du...
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MichaelL's avatar
MichaelL
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2 months ago

Hi VenT_Altera​,

although we currently have a workaround, it would be very helpful to know, if empty words are allowed or not. 

Best Regards,

Michael

VenT_Altera's avatar
VenT_Altera
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2 months ago

Hi MichaelL 

I understand your concern, and I apologize for the delayed response. I hope this answers your question.

Does the IP-Core not allow for a first word to be completely disabled? 
No. Based on the user guide description for txs_byteenable_i[<w> -1:0], the first and final data phases of a burst can have other valid values. For the 128-bit interface,  the following patterns are legal for the first and final word:
○ 16'hF000
○ 16'h0F00
○ 16'h00F0
○ 16'h000F
○ 16'hFF00
○ 16'h0FF0
○ 16'h00FF
○ 16'hFFF0
○ 16'h0FFF
○ 16'hFFFF 

Therefore, 16'h0000 is not a legal pattern for the first word.

Thanks.
Best Regards,
Ven