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Serge93
Occasional Contributor
Occasional ContributorF-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
Hello Support, I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point se...
You may need to recheck your design if a given valid is not seen by the IP.
Here is how a F-Tile RP reads another FPGA's VID.
Serge93Occasional Contributor
Occasional ContributorHello Rong,
When I trig on tx_st_valid, it never trigs.
Do you have a PCIe specialist I can have access ?
Thanks.
Serge
RongY_altera
Contributor
ContributorYou may need to recheck your design if a given valid is not seen by the IP.
Here is how a F-Tile RP reads another FPGA's VID.
- Serge93
Thank you Rong.
Serge
