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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
1 month ago
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F-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer

Hello Support, I am using the Agilex 7F Dev Kit with F-Tile configured in Root Port Gen3x4. When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh, the end point se...
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  • RongY_altera's avatar
    RongY_altera
    1 month ago

    You may need to recheck your design if a given valid is not seen by the IP.

    Here is how a F-Tile RP reads another FPGA's VID.
     

RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 month ago

Hi Serge,

 

When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh

>>This doesn't look right. For a BAR test, I think you should use MWr and MRd.

 

Regards,

Rong

 

RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 month ago

Thanks for the clarification. I misunderstood your request in the previous message.

 

From the stp, you were reading addr 0x01000010, not 0x10.

 

 

Regards,

Rong

 

  • Serge93's avatar
    Serge93
    Icon for Occasional Contributor rankOccasional Contributor
    1 month ago

    Hello Rong,

    When using a Configuration Write or Read Request the address is compose of : Bus Number(7:) & Device Nb(7:0) & Ext_Reg(7:0) & reg Nb(7:0).

    So what you see is the Bus Number=01h and Reg Nb=10h.

    By the way, I have the same behaviour with the address=00h (Device ID & Vendor ID) in the Configuration Space.

    Thanks for help.

    Serge

    • Serge93's avatar
      Serge93
      Icon for Occasional Contributor rankOccasional Contributor
      1 month ago

      Hello Rong,

      Any news, I am blocked now. Can you have the help from another person ?

      Thank you.
      Serge

      • RongY_altera's avatar
        RongY_altera
        Icon for Contributor rankContributor
        1 month ago

        I'm trying to setup a F-Tile RP test env to check.