Forum Discussion
Occasional ContributorF-Tile PCIe Root Port 1x Gen3x4 - Configuration Read Type 0 receives no answer
You may need to recheck your design if a given valid is not seen by the IP.
Here is how a F-Tile RP reads another FPGA's VID.
ContributorHi Serge,
When I am doing a Configuration Write Type 0 to write the End Point BAR0 with FFFF_FFFFh
>>This doesn't look right. For a BAR test, I think you should use MWr and MRd.
Regards,
Rong
Serge93Hello Rong,
Nice to see you again.
BAR0 in address 10h, is in the Configuration Space not in the Memory Space, so you have to use a Configuration Access. I am using the same access with my Agilex7i-R-Tile board and it is working. So this is very strange it is not working on the Agilex-7F board.
Thanks for help.
Serge- RongY_altera
Thanks for the clarification. I misunderstood your request in the previous message.
From the stp, you were reading addr 0x01000010, not 0x10.
Regards,
Rong
- Serge93
Hello Rong,
When using a Configuration Write or Read Request the address is compose of : Bus Number(7:) & Device Nb(7:0) & Ext_Reg(7:0) & reg Nb(7:0).
So what you see is the Bus Number=01h and Reg Nb=10h.
By the way, I have the same behaviour with the address=00h (Device ID & Vendor ID) in the Configuration Space.
Thanks for help.
Serge
- Serge93
Hello Rong,
Any news, I am blocked now. Can you have the help from another person ?
Thank you.
Serge
