DDR2 license Question
The customer obtained the DDR2 license through the Altera website. Does this IP license have any time limitation or other usage restrictions? When generating the project for the EP4CE75U19I7N device, Quartus only generates project.sof and does not generate project_time_limited.sof.
User controlled burst refresh
Hi, I have a problem regarding DDR3 EMIF IP can't bursting user control refresh. I am debugging my EMIF test design on Cyclone 10 GX development board. The situation is that it takes long time to get mmr_refresh_ack response. Below is my environment: Quartus Prime Pro 23.2 on Windows 11 External Memory Interfaces Intel Cyclone 10 FPGA IP, altera_emif_c10 19.1.1 Cyclone 10 GX FPGA Development Kit (Power Solution 1) DK-DEV-10CX220-A Cyclone 10 GX 10CX220YF780E5G First of all, I have a question about the description of the user guide. I would like to fix my design after question was solved. I am referring External Memory Interfaces Cyclone 10 GX FPGA IP User Guide Updated for Quartus Prime Design Suite: 24.1 IP Version: 19.1.2. 1. In page 84, Table 4.4.13 for mmr_refresh_req states that Controller clears this bit to 0 when the refresh is executed. This is inconsistent for the description: Page 223, 9.4.6.1 Back-to-Back User-Controlled Refresh Usage: The waveform instruct user to clear mmr_refresh_req before set mmr_refresh_req again at reference time (5). I guess this waveform explains back-to-back user controlled refresh so, the next refresh request is expected tRFC after reference time (4). My question is: Should I clear the mmr_refresh_req register before back-to-back next refresh request? 2. In page 223, --- Note: If you enable the auto-precharge control, you must ensure that the average periodic refresh requirement is met, because the controller does not issue any refreshes until you instruct it to. --- What happens if I disable the auto-precharge control? In this case, are both IP planned refresh and user controlled refresh happens? 3. There are two enable user refresh controls in the user guide: 1) IP parameter of Enable User Refresh Control 2) cfg_user_rfsh_en register inside the IP What is the relationship of them? Does the IP parameter define initial state of cfg_user_rfsh_en register? Is the logical AND condition needed for the user controlled refresh? 4. In page 78, table 4.4. Cyclone 10 GX Memory Mapped Register (MMR) Tables: The cfg_user_rfsh_en register is missing. Do I need to handle this register? Masaru
Cyclone-V SCFIFO with M10K/MLAB memory - adding ECC
Hi, I am working with a Cyclone-V 5CSXFC6C6U2317 FPGA and using the MegaWizard's IP FIFO SCFIFO in it. The SCFIFO is for custom logic and is outside of the HPS/ARM/Nios sub-system. My Quartus is 23.1 Prime Standard Edition. From the "FIFO IP User Guide for Quartus® Prime Design Suite: 25.1.1" it looks like I can enable (hard, memory-build in) ECC protection only for Arria 10 devices with M20K memory. My Cyclone-V has M10K memory (and Auto and MLAB memory) . It should be possible for me to add a soft-ECC module in the fabric, either inside the SCFIFO wrapper (from MegaWizard), or outside the SCFIFO wrapper. Has anyone done (or seen in Altera's Github) such a soft-ECC module ( for example using a Hamming SEC-DED (24,16) code or similar) ?
DCFIFO encounters errors during compilation
Hello Guys, We use DC FIFO to buffer data between user logic and transceivers. We got 32 error infomations (the fifo depth is 32) during compilation: Error(15465): WYSIWYG primitive "u_xcvr_cba|u_RxDataReg|USR_RXD_FIFO|fifo_0|dcfifo_component|auto_generated|fifo_ram|ram_block5a4" has clk0 port that must be connected Could anyone guide us to resolve this issue? Thanks
DDR4 Problem Migrating from Arria 10 016 to 048
We have a board design that supports an F29 package Arria 10. It has two DDR4 interfaces running at an 1866 data rate. In the past an 016 chip with DDR4-2400 ICs worked fine. We needed more logic so we migrated to an 048. Because of parts availability we had to migrate to DDR-3200 ICs. The board layout has not changed and we believe the various power supplies and clocks are working fine. The 048 design fails calibration and won't even allow running "EMIF toolkit - Create Memory Interface." It hangs and times out. If I turn off address / command leveling the design still fails calibration but now I can create a memory interface and see the calibration results which show a complete failure with write and read margins. The design is badly broken but we don't know if it is the 048 or DDR4, or a combination of both. The DDR4 IP was regenerated and adjusted for the DDR4-3200 ICs. We do see PLL lock with signaltap and can actually run Efficiency monitor. So the core is supplying a good clock to the fabric. Any suggestions are welcome! Thanks, Mike
Agilex 5 EMIF-LPDDR4, AXI4 Read-Write Starvation Issue
Hello, I have a Agilex 5 design (based on the Terasic DE25_Nano) implementing the LPDDR4-EMIF. My own IP (acting as a AXI4 Manager) is connected to the AXI4 Subordinate port of the EMIF to read and write onto the LPDDR. All is working perfectly, but in some R/W pattern cases where the write channel issues many consecutive commands, the Read channel is starved until the end of the write sequence of commands, which means no valid data are received before a very long (unacceptable) time. Obviously the EMIF gives the priority to the write channel which lead to read starvation. Regarding the EMIF Parameters Settings, I tested the three "Controller Performance Profiles" without any success. I also tested several set of values for the "Data Bus Turnaround Times" settings without any success too. Ideally, I would expect either disabling Reordering or configuring a Starvation counter limit, but these parameters do not exist in the Agilex 5 EMIF IP. As a remark, I noticed these settings (Enable Reordering + Starvation limit) exist in the Agilex 7 EMIF IP. Regarding the External Memory Interfaces (EMIF) IP User Guide for Agilex 5 FPGAs and SoCs, section "Features of the Agilex 5 Hard Memory Controller" Table 30, I noticed there is a parameter named "Starvation counter" but there is no explanation how to configure it. In summary, I do not see any way to have control over Reordering/Starvation with Agilex 5 EMIF-LPDDR4. Thank you in advance for any suggestion. Regards
MSGDMA: Is Linux Driver Mandatory? Using devmem2 & F2SDRAM Bridge
Hello everyone, I am currently working on an MSGDMA implementation. I have verified that I can read the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode. I have two specific questions regarding this setup: 1、Is configuring the MSGDMA Linux kernel driver a mandatory condition for the hardware to function correctly? Is it possible to bypass the driver and configure the MSGDMA to start data transfer directly using devmem2 (user-space access)? 2、I noticed that some implementations write to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM link, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?Agilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP
Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？
Is Agilex 5 DDR4 calibration support Command Bus training?
May I know if Agilex 5 DDR4 calibration support command bus training? This info is not in the Agilex 5 EMIF IP UG, but it is in the Agilex 7 EMIF IP UG. Can you confirm if Agilex 5 DDR4 support or not? For your reference, below is the calibration stage for Agilex 7 Thanks.
