MSGDMA: Is Linux Driver Mandatory? Using devmem2 & F2SDRAM Bridge
Hello everyone, I am currently working on an MSGDMA implementation. I have verified that I can read the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode. I have two specific questions regarding this setup: 1、Is configuring the MSGDMA Linux kernel driver a mandatory condition for the hardware to function correctly? Is it possible to bypass the driver and configure the MSGDMA to start data transfer directly using devmem2 (user-space access)? 2、I noticed that some implementations write to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM link, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?Agilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP
Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？
Is Agilex 5 DDR4 calibration support Command Bus training?
May I know if Agilex 5 DDR4 calibration support command bus training? This info is not in the Agilex 5 EMIF IP UG, but it is in the Agilex 7 EMIF IP UG. Can you confirm if Agilex 5 DDR4 support or not? For your reference, below is the calibration stage for Agilex 7 Thanks.Unable to simulate DDR3 controller
Hello, I have a design with DDR3 and I am using the Altera DDR3 SDRAM Controller with UniPHY for Intel FPGA IP to interface with it and I want to run a simulation that involves the controller and the actual DDR3 memory model. I have never had to run a simulation involving an external DDR memory so I want to start by running a simulation of the example design for the IP. When configuring the IP, at the end, I enable the "Generate Example Design" and I see the respective folders _sim and _example_design created. This completes without errors. Inside the _example_design folder, there are two additional ones: example_project and simulation. Inside the exaple_project folder, I see a QPF file. I can open that from Quartus as "Open Project". However, after clicking "Analysis and Synthesis" and double clicking on the top level module, I get this error: Trying to run Tools-> RTL Simulation doesn't give any errors but Questa never launches. I am using Quartus 23.1 on a Windows 11 machine. Any help would be appreciated. Juan Escobedo, Ph.D.
Unexpected behavior of DDR3 controller on Arria V GZ when using manual refresh
deHello, I am using the DDR3 controller IP on an Arria V GZ FPGA and I am noticing a different behavior when issuing a refresh request using the manual refresh interface. When issuing the refresh after a read request, the ready signal stays asserted and rdata_valid is asserted after the next read request and stays asserted for the expected interval: However, when issuing the refresh request after a write, the ready signal is de-asserted. Then, after it is re-asserted, and we issue the next read request, the rdata_valid signal starts "glitching": Can anyone point where can I find further information about this behavior? I checked the DDR3 SDRAM High-Performance Controller User Guide and External Memory Interface Handbook Volume 2: Design Guidelines For UniPHY-based Device Families documents with no luck. Any help would be appreciated. Thanks beforehand, Juan Escobedo, Ph.D.Over 4GB PCIe BAR Size Issue
Hi, I created a design that utilizes the Arria 10 Hard IP and an EMIF. On my board, I have 8GB of DDR memory, and I wanted to connect one of the PCIe BARs to the EMIF so I could read from and write to the DDR. I encountered an issue where the OS (I tried both Windows and Linux) detects the BAR size but cannot use it. I was unable to read from or write to this BAR. When I used the Address Span Extender to reduce the BAR size to 2GB, I was able to read and write. However, when I increased it to 4GB or above, it no longer worked. I also tried enabling "Above 4G Decoding" and "Resizable BAR" in the BIOS, but it made no difference. Has anyone else encountered this issue?
