DDR4 Problem Migrating from Arria 10 016 to 048
We have a board design that supports an F29 package Arria 10. It has two DDR4 interfaces running at an 1866 data rate. In the past an 016 chip with DDR4-2400 ICs worked fine. We needed more logic so we migrated to an 048. Because of parts availability we had to migrate to DDR-3200 ICs. The board layout has not changed and we believe the various power supplies and clocks are working fine. The 048 design fails calibration and won't even allow running "EMIF toolkit - Create Memory Interface." It hangs and times out. If I turn off address / command leveling the design still fails calibration but now I can create a memory interface and see the calibration results which show a complete failure with write and read margins. The design is badly broken but we don't know if it is the 048 or DDR4, or a combination of both. The DDR4 IP was regenerated and adjusted for the DDR4-3200 ICs. We do see PLL lock with signaltap and can actually run Efficiency monitor. So the core is supplying a good clock to the fabric. Any suggestions are welcome! Thanks, Mike
Cyclone-V SCFIFO with M10K/MLAB memory - adding ECC
Hi, I am working with a Cyclone-V 5CSXFC6C6U2317 FPGA and using the MegaWizard's IP FIFO SCFIFO in it. The SCFIFO is for custom logic and is outside of the HPS/ARM/Nios sub-system. My Quartus is 23.1 Prime Standard Edition. From the "FIFO IP User Guide for Quartus® Prime Design Suite: 25.1.1" it looks like I can enable (hard, memory-build in) ECC protection only for Arria 10 devices with M20K memory. My Cyclone-V has M10K memory (and Auto and MLAB memory) . It should be possible for me to add a soft-ECC module in the fabric, either inside the SCFIFO wrapper (from MegaWizard), or outside the SCFIFO wrapper. Has anyone done (or seen in Altera's Github) such a soft-ECC module ( for example using a Hamming SEC-DED (24,16) code or similar) ?
Agilex 5 EMIF-LPDDR4, AXI4 Read-Write Starvation Issue
Hello, I have a Agilex 5 design (based on the Terasic DE25_Nano) implementing the LPDDR4-EMIF. My own IP (acting as a AXI4 Manager) is connected to the AXI4 Subordinate port of the EMIF to read and write onto the LPDDR. All is working perfectly, but in some R/W pattern cases where the write channel issues many consecutive commands, the Read channel is starved until the end of the write sequence of commands, which means no valid data are received before a very long (unacceptable) time. Obviously the EMIF gives the priority to the write channel which lead to read starvation. Regarding the EMIF Parameters Settings, I tested the three "Controller Performance Profiles" without any success. I also tested several set of values for the "Data Bus Turnaround Times" settings without any success too. Ideally, I would expect either disabling Reordering or configuring a Starvation counter limit, but these parameters do not exist in the Agilex 5 EMIF IP. As a remark, I noticed these settings (Enable Reordering + Starvation limit) exist in the Agilex 7 EMIF IP. Regarding the External Memory Interfaces (EMIF) IP User Guide for Agilex 5 FPGAs and SoCs, section "Features of the Agilex 5 Hard Memory Controller" Table 30, I noticed there is a parameter named "Starvation counter" but there is no explanation how to configure it. In summary, I do not see any way to have control over Reordering/Starvation with Agilex 5 EMIF-LPDDR4. Thank you in advance for any suggestion. Regards
MSGDMA: Is Linux Driver Mandatory? Using devmem2 & F2SDRAM Bridge
Hello everyone, I am currently working on an MSGDMA implementation. I have verified that I can read the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode. I have two specific questions regarding this setup: 1、Is configuring the MSGDMA Linux kernel driver a mandatory condition for the hardware to function correctly? Is it possible to bypass the driver and configure the MSGDMA to start data transfer directly using devmem2 (user-space access)? 2、I noticed that some implementations write to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM link, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?Agilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP
Hi all, I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR. I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？
Is Agilex 5 DDR4 calibration support Command Bus training?
May I know if Agilex 5 DDR4 calibration support command bus training? This info is not in the Agilex 5 EMIF IP UG, but it is in the Agilex 7 EMIF IP UG. Can you confirm if Agilex 5 DDR4 support or not? For your reference, below is the calibration stage for Agilex 7 Thanks.Unable to simulate DDR3 controller
Hello, I have a design with DDR3 and I am using the Altera DDR3 SDRAM Controller with UniPHY for Intel FPGA IP to interface with it and I want to run a simulation that involves the controller and the actual DDR3 memory model. I have never had to run a simulation involving an external DDR memory so I want to start by running a simulation of the example design for the IP. When configuring the IP, at the end, I enable the "Generate Example Design" and I see the respective folders _sim and _example_design created. This completes without errors. Inside the _example_design folder, there are two additional ones: example_project and simulation. Inside the exaple_project folder, I see a QPF file. I can open that from Quartus as "Open Project". However, after clicking "Analysis and Synthesis" and double clicking on the top level module, I get this error: Trying to run Tools-> RTL Simulation doesn't give any errors but Questa never launches. I am using Quartus 23.1 on a Windows 11 machine. Any help would be appreciated. Juan Escobedo, Ph.D.
Unexpected behavior of DDR3 controller on Arria V GZ when using manual refresh
deHello, I am using the DDR3 controller IP on an Arria V GZ FPGA and I am noticing a different behavior when issuing a refresh request using the manual refresh interface. When issuing the refresh after a read request, the ready signal stays asserted and rdata_valid is asserted after the next read request and stays asserted for the expected interval: However, when issuing the refresh request after a write, the ready signal is de-asserted. Then, after it is re-asserted, and we issue the next read request, the rdata_valid signal starts "glitching": Can anyone point where can I find further information about this behavior? I checked the DDR3 SDRAM High-Performance Controller User Guide and External Memory Interface Handbook Volume 2: Design Guidelines For UniPHY-based Device Families documents with no luck. Any help would be appreciated. Thanks beforehand, Juan Escobedo, Ph.D.
