API calls failed while running PCIe DMA transfer example design
Hi, I was working the PCIe DMA transfer example design for Arria 10. I have added a counter custom IP which counts upto 1000, and An Avalon FIFO IP with the design. My intention is to write the data created in counter to DDR4 and then use the DMA API call (provided by Terasic in Demonstrations/PCIe_SW_KIT/Windows/PCIe_DDR4/PCIE_DDR4.cpp) to read them from PC. Even if I follows the steps given in the User manual of DE5a_DDR4_NET (attaching the manual. The chapter-7 section 7.6 is what I was following), the DMA API calls to read data fails. I would like to know why I could not run Read DMA API from the PC. The It would be great if someone could give any helping hand. I am attaching the error message (Crash_op.PNG). I am just listing the procedure I followed, 1. Installed both DDR4 2400 4GB SODIMM on the FPGA board. 2. Connected the FPGA board with PC through PCIe. 3. Configured FPGA with DE5A_NET.sof (here the design .sof having PCIe DMA transfer example design + Avalon FIFO + Counter custom IP) by executing the test.bat. 4. Restart Windows 4. I could see the PCIe driver in the device manager (Windows has detected the FPGA Board). 7. Executed the PCIE_DDR4.exe. Then in the menu putting the options 3, 4 and 5 gives the failure. FYI: I have been using Quartus Prime Pro 18.1 in Windows 10.
timing_error_for_pll_afi_clock_on_ddr3_ip_controller
Hi Team, I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setting) and uses afi_clock(200 Mhz) to connect the clock of other interfaces. pll_clock of ddr interface is 50 Mhz. connected from the osciallator in the board. Nios processor also connected with afi clock only (200 Mhz) For this design , i am getting pll_afi_clock setup time violation. i have attached the timing report. PLease give solution for this.Addressing the Greatest Memory and Compute Challenges with Intel® Agilex™ M-Series FPGAs
We are enabling our customers to achieve higher performance with better power efficiency across all end markets and applications with our flagship Intel® Agilex™ FPGA family. We continue to build the momentum, with the Intel® Agilex™ M-Series family variant.Timing constraints of Intel IPs
Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP cores have their own timing constraints with their own .sdc files. But it seems that these constraints are not applied when I compiled my design. And I cannot find the generated .sdc file either. Do you know how I can generate that .sdc file and add it into the project by (not sure about this part) Assignments -> Settings -> Timing Analyzer -> ? Thanks in advance
Exploring why GSFI IP Core repeats sending command and address for each 4-byte data in Page Program
Dear Intel Support Team, We're working on two projects to communicate with Micron Flash Memory. The first one called the SPI project, uses the SPI 4-wire IP core and SPI driver. In the second project, known as the GSFI project, we're using the Generic Serial Flash Interface IP Core with the GSFI HAL driver. The protocol used in the GSFI project is Standard SPI. In the SPI project, when we use the alt_avalon_spi_command() function to write a page of Flash memory, everything goes smoothly. The Chip-Select signal goes low, then we send the Page Program command, address, and data. Each byte of data is sent to the flash memory one at a time. But in the GSFI project, when we use the intel_gsfi_write_block() function to write a page in the Flash memory, things are a bit different. For every 4-byte data segment, the GSFI core first sends a Write Enable command. Then it sends the Page Program command, address, and the 4-byte data. After that, it checks the Status Register. This process repeats for each 4-byte segment, creating a lot of overhead. We're looking for help in understanding why the GSFI core behaves differently compared to the simpler SPI method used in the SPI project. In fact, we are wondering why GSFI IP Core sends the Page Program command and address for each 4-byte data, instead of sending data as a burst, as explained above. Note: We're using Intel Quartus Prime Pro Edition on Agilex 7 SoC.
DDR2 clock from PLL out
hello I am using Arria ii gx FPGA in Nios processor.altmemphy IP and our board main clock is 50 mhz i want to know about interfacing between DDR2 clock to FPGA my customize board connected the DDR2 clock with the differential pair pin AJ16 and AJ15. My question is about the PLL dedicated pin how to create or assign dedicated pin in my top level design Thanks Nomefacing 12002 error while upgrading qsys design from 13.0 to 22.1 quartus
Hi Team, i have upgrading the qsys design from 13.0 to 22.1 . during upgradation, added ddr3 ip and generated the qsys. while synthesizing the design , facing 12002 error. whether do i miss any steps in qsys? i am new to qsys design and please help me to resolve this issue? Attached the screenshot of error.Critical Warning: PLL clock
Hello We are porting Arria ii gx Nios processor in ddr2 IP and ddr2 clock feed from PLL C0 and PLL IP directly connected from FPGA clock I am facing some below critical warnings I google this kind of warnings I found this is PLL IP main In clock issue maybe we have to make or add something in SDC file please help us how to add clock arrangement in SDC file Critical Warning: PLL clock inst0_nios_cpu|lms_ctr_inst0|ddr2_1|lms_ctr_ddr2_1_controller_phy_inst|lms_ctr_ddr2_1_phy_inst|lms_ctr_ddr2_1_phy_alt_mem_phy_inst|clk|full_rate.pll|altpll_component|auto_generated|pll1|clk[4] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Thanks Nome