Can we generate EMIF DDR4 without mem_alert_n or not connect the emif_alert_n in the instantiation

Hi BB,

The alert_n signal is required for DDR4 interface.

There is no other option. You need to move the DQ group from A/C IO Bank to place the alert_n pin in IO Lane 3.

Regards,

Adzim

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Hi Adzim,

Thanks for the earlier response confirming that mem_alert_n signal is required for the implementation.

Again referring to the earlier attached pdf with the pin out for the two EMIF interfaces, I am trying to increase the accessible memory size from 32 GB to 64GB with the existing pinout with minimal changes i.e. use only 3 IO Banks per memory IO and ignore the 7th IO bank which has IOs from both EMIF. The mem_alert_n for both the interfaces (Bank 2M for MC0 and Bank 2H for MC1) is located at the pin for mem_a[17]. I moved the mem_a[17] to the mem_alert_n pin locations and moved the mem_alert_n to the rzq pin location for both EMIFs. This leaves 2 RZQ to be mapped and only 1 pin location available in bank 2K (PIN_AJ68).

As the RZQ pin is just a resistor grounded, is it possible for two EMIF to use teh same pin location for RZQ.
OR
Each IO bank has one pin for IO_RZQ_.......... Is it possible to use any other pin with the same bank for RZQ i.e. both EMIF interfaces have RZQ in the same bank? one can be at the designated pin location for RZQ and other at any of the other available pins within the bank.
OR
Can the RZQ pin be mapped to some other bank not adjacent to EMIF (BANK3d) but have a different IO standard spec as ther other pins in that bank are not 1.2 v standard.

In short is there any way to map the extra RZQ and get the 64 GB with minimal pin reroute (estimating 6).

the other idea of full size access with 4 IO banks per EMIF is no go as it requires complete boad reroute.

Best,
BB

Hi BB,

"As the RZQ pin is just a resistor grounded, is it possible for two EMIF to use teh same pin location for RZQ"

• I haven't try to map 2 RZQ port to one pin location as it not a recommended way to place the RZQ pin but you can try it on Quartus and check if the Quartus can Fit the placement.
• I cannot guarantee the functionality of DDR to work well or verify on hardware and you need to take your own risk to have this placement.

"Each IO bank has one pin for IO_RZQ_.......... Is it possible to use any other pin with the same bank for RZQ i.e. both EMIF interfaces have RZQ in the same bank? one can be at the designated pin location for RZQ and other at any of the other available pins within the bank."

• Cannot, need to use the designate location.

"Can the RZQ pin be mapped to some other bank not adjacent to EMIF (BANK3d) but have a different IO standard spec as ther other pins in that bank are not 1.2 v standard."

• UG has stated that the RZQ pin can be placed in any I/O bank in same I/O column that has same voltage standard.
• https://www.intel.com/content/www/us/en/docs/programmable/683741/24-1-19-2-8/general-guidelines-39744-01.html

I'm have a doubt that the alert_n pin can place in RZQ pin location.

You should check this in Quartus Fitter compilation.

Regards,

Adzim

Hi BB,

There is no hardware validation can be done to verify that this configuration is working because the alert_n signal is not placed in RZQ pin location on the boards, and this placement is not a recommendation of RZQ pin.

If you find that the Quartus can compile the design with the pin placement and config, then most likely the design might be working.

But still, you need to take your own risk since this is not a recommended way.

Regards,

Adzim

Hi Adzim,

I understand that there is current hardware to validate the placement of alert_n pin on recommended rzq pin and also for two RZQ ports driven by one pin. Hence i request you to please reach out to the EMIF IP design team and share their insights.

Best,

BB

Hi BB,

You can share the RZQ pin with two RZQ ports but the VCCIO need to be the same.

If not, the calibration will fail.

For alert_n placement, there is not much restriction.

You may use your current plan to fix your problem.

Regards,

Adzim