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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Can we generate EMIF DDR4 without mem_alert_n or not connect the emif_alert_n in the instantiation

Hi Please refer the attached png/pdf of the pin map of two EMIF instantiations in our design. The initial board design shared a FPGA IO bank for some address/command signals of the two instances, r...
Memory
  • BKB's avatar
    BKB
    1 year ago
    Thanks Adzim.

    Best,

    BB

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi BB,

There is no hardware validation can be done to verify that this configuration is working because the alert_n signal is not placed in RZQ pin location on the boards, and this placement is not a recommendation of RZQ pin.

If you find that the Quartus can compile the design with the pin placement and config, then most likely the design might be working.

But still, you need to take your own risk since this is not a recommended way.

Regards,

Adzim