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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Can we generate EMIF DDR4 without mem_alert_n or not connect the emif_alert_n in the instantiation

Hi Please refer the attached png/pdf of the pin map of two EMIF instantiations in our design. The initial board design shared a FPGA IO bank for some address/command signals of the two instances, r...
Memory
  • BKB's avatar
    BKB
    1 year ago
    Thanks Adzim.

    Best,

    BB

BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Hi Adzim,

I understand that there is current hardware to validate the placement of alert_n pin on recommended rzq pin and also for two RZQ ports driven by one pin. Hence i request you to please reach out to the EMIF IP design team and share their insights.

Best,

BB

  • BKB's avatar
    BKB
    Icon for Occasional Contributor rankOccasional Contributor
    1 year ago

    Hi Adzim,

    I understand that there is NO current hardware to validate the placement of alert_n pin on recommended RZQ pin and also for two RZQ ports driven by one pin. Hence I request that you please reach out to the EMIF IP design team and share their insights.

    Best,

    BB