Occasional ContributorBest,
BB
Regular ContributorHi BB,
"As the RZQ pin is just a resistor grounded, is it possible for two EMIF to use teh same pin location for RZQ"
"Each IO bank has one pin for IO_RZQ_.......... Is it possible to use any other pin with the same bank for RZQ i.e. both EMIF interfaces have RZQ in the same bank? one can be at the designated pin location for RZQ and other at any of the other available pins within the bank."
"Can the RZQ pin be mapped to some other bank not adjacent to EMIF (BANK3d) but have a different IO standard spec as ther other pins in that bank are not 1.2 v standard."
I'm have a doubt that the alert_n pin can place in RZQ pin location.
You should check this in Quartus Fitter compilation.
Regards,
Adzim
Occasional Contributor"I haven't try to map 2 RZQ port to one pin location as it not a recommended way to place the RZQ pin but you can try it on Quartus and check if the Quartus can Fit the placement."
Quartus completed the build with 2 RZQ ports to one pin location for our existing board and the proposed one.
"I cannot guarantee the functionality of DDR to work well or verify on hardware and you need to take your own risk to have this placement"
The build seems to be working in the initial tests. If you cannot guarantee functionality, could you please confirm with internal experts if this is a valid implementation and the design would work going forward
"I'm have a doubt that the alert_n pin can place in RZQ pin location. You should check this in Quartus Fitter compilation."
Quartus implemented the design with the alert_n pin in the rzq location. In fact that's quartus plan/fits preferred location when the address command pins are fully occupied or when we run the build without assigned pin locations. Look at the attached snapshot from the IP generation window where alert_n pin location can be selected. The tool gives error for selection "I/O lane with DQS group" but works for other options.
I ran an example build with memory configurations occupying the whole address/command bank. In this case the rzqin pin is placed in an bank other than with address/command IO. In our current board, alert_n was at the location for addrress[17]. So with that occupied for increasing memory size, the rzq pin was the only available pin for alert_n.
I request that you please confirm internally that this option can work. i.e. alert_n at rzq location in address/command and one rzq driving two emif rzq input.
Best,
BB
