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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Can we generate EMIF DDR4 without mem_alert_n or not connect the emif_alert_n in the instantiation

Hi Please refer the attached png/pdf of the pin map of two EMIF instantiations in our design. The initial board design shared a FPGA IO bank for some address/command signals of the two instances, r...
Memory
  • BKB's avatar
    BKB
    1 year ago
    Thanks Adzim.

    Best,

    BB

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi BB,


The alert_n signal is required for DDR4 interface.


There is no other option. You need to move the DQ group from A/C IO Bank to place the alert_n pin in IO Lane 3.


Regards,

Adzim