Can we generate EMIF DDR4 without mem_alert_n or not connect the emif_alert_n in the instantiation

Hi Adzim,

Thanks for the earlier response confirming that mem_alert_n signal is required for the implementation.

Again referring to the earlier attached pdf with the pin out for the two EMIF interfaces, I am trying to increase the accessible memory size from 32 GB to 64GB with the existing pinout with minimal changes i.e. use only 3 IO Banks per memory IO and ignore the 7th IO bank which has IOs from both EMIF. The mem_alert_n for both the interfaces (Bank 2M for MC0 and Bank 2H for MC1) is located at the pin for mem_a[17]. I moved the mem_a[17] to the mem_alert_n pin locations and moved the mem_alert_n to the rzq pin location for both EMIFs. This leaves 2 RZQ to be mapped and only 1 pin location available in bank 2K (PIN_AJ68).

As the RZQ pin is just a resistor grounded, is it possible for two EMIF to use teh same pin location for RZQ.
OR
Each IO bank has one pin for IO_RZQ_.......... Is it possible to use any other pin with the same bank for RZQ i.e. both EMIF interfaces have RZQ in the same bank? one can be at the designated pin location for RZQ and other at any of the other available pins within the bank.
OR
Can the RZQ pin be mapped to some other bank not adjacent to EMIF (BANK3d) but have a different IO standard spec as ther other pins in that bank are not 1.2 v standard.

In short is there any way to map the extra RZQ and get the 64 GB with minimal pin reroute (estimating 6).

the other idea of full size access with 4 IO banks per EMIF is no go as it requires complete boad reroute.

Best,
BB